Nvidia Jetson Orin NX Design Manual page 29

Module Pin
Pin # Name Orin Signal
HS_UPHY0_L3_RX_
169 PCIE1_RX0_P
P
HS_UPHY0_L3_TX_
172 PCIE1_TX0_N
N
174 PCIE1_TX0_P HS_UPHY0_L3_TX_P
GP178_PCIE1_RST_
183 PCIE1_RST*
N
PCIE1_CLKRE GP177_PCIE1_
182
Q* CLKREQ_N
173 PCIE1_CLK_N SF_PCIE1_CLK_N
175 PCIE1_CLK_P SF_PCIE1_CLK_P
HS_UPHY2_L0_RX_
40 CSI4_D2_N
N
HS_UPHY2_L0_RX_
42 CSI4_D2_P
P
HS_UPHY2_L1_RX_
58 CSI4_D1_N
N
HS_UPHY2_L1_RX_
60 CSI4_D1_P
P
HS_UPHY2_L0_TX_
46 CSI4_D0_N
N
48 CSI4_D0_P HS_UPHY2_L0_TX_P PCIe #2 Transmit 0+ (PCIe Ctrl #7 Lane 0)
HS_UPHY2_L1_TX_
64 CSI4_D3_N
N
66 CSI4_D3_P HS_UPHY2_L1_TX_P
52 CSI4_CLK_N SF_PCIE7_CLK_P
54 CSI4_CLK_P SF_PCIE7_CLK_N
GP188_PCIE7_RST_
219 SDMMC_DAT0
N
GP187_PCIE7_
221 SDMMC_DAT1
CLKREQ_N
229 SDMMC_CLK SF_PCIE9_CLK_P
227 SDMMC_CMD SF_PCIE9_CLK_N
GP192_PCIE9_RST_
223 SDMMC_DAT2
N
GP191_PCIE9_
225 SDMMC_DAT3
CLKREQ_N
GP185_PCIE_WAKE
179 PCIE_WAKE*
_N
HS_UPHY0_L0_RX_
161 USBSS_RX_N
N
PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX
Usage and Description
PCIe #1 Transmit 0 (PCIe Ctrl #1 Lane 0)
PCIe #1 Reset (PCIe Ctrl #1). 4.7kΩ pull-up
to 3.3V on the module.
PCIE #1 Clock Request (PCIe Ctrl #1).
47kΩ pull-up to 3.3V on the module.
PCIe #1 Reference Clock (PCIe Ctrl #1)
PCIe 2 Receive 0– (PCIe Ctrl #7 Lane 0)
PCIe 2 Receive 0+ (PCIe Ctrl #7 Lane 0)
PCIe #2 Receive 1– (PCIe Ctrl #7 Lane 1) or
PCIe #3 Receive 0– (PCIe Ctrl #9 Lane 0)
PCIe #2 Receive 1+ (PCIe Ctrl #7 Lane 1) or
PCIe #3 Receive 0+ (PCIe Ctrl #9 Lane 0)
PCIe #2 Transmit 0– (PCIe Ctrl #7 Lane 0)
PCIe #2 Transmit 1– (PCIe Ctrl #7 Lane 1)
or PCIe #3 Transmit 0– (PCIe Ctrl #9 Lane
0)
PCIe #2 Transmit 1+ (PCIe Ctrl #7 Lane 1)
or PCIe #3 Transmit 0+ (PCIe Ctrl #9 Lane
0)
PCIe #2 Reference Clock– (PCIe Ctrl #7)
PCIe #2 Reference Clock+ (PCIe Ctrl #7)
PCIe #2 Reset (PCIe Ctrl #7). 4.7kΩ pull-up
to 3.3V on the module.
PCIE #2 Clock Request (PCIe Ctrl #7).
47kΩ pull-up to 3.3V on the module.
PCIe #3 Reference Clock– (PCIe Ctrl #9)
PCIe #3 Reference Clock+ (PCIe Ctrl #9)
PCIe #3 Reset (PCIe Ctrl #9). 4.7kΩ pull-up
to 3.3V on the module.
PCIE #3 Clock Request (PCIe Ctrl #9).
47kΩ pull-up to 3.3V on the module.
PCIe Wake. 47kΩ pull-up to 3.3V on the
module.
USB SS Receive (USB 3.2 Port #0)
USB and PCIe
Recommended
Usage Direction
Output
PCIe x1
conn/device (i.e.
Output
M.2 Key E)
Bidir
Output
Input
Input
Output
Output
Output
Output
PCIe x2 (Ctrl #7)
or 2 x PCIe x1
(Ctrl #7 and Ctrl
Output
#9)
Output
Input
Input
Output
Bidir
Output
Output
PCIe x1 (Ctrl #3)
Output
Bidir
Shared between
Input
PCIe interfaces.
Input
DG-10931-001_v0.1 | 21
Pin Type
PCIe PHY
Open
Drain 3.3V
Open
Drain 3.3V
PCIe PHY
PCIe PHY
PCIe PHY
PCIe PHY
PCIe PHY
PCIe PHY
PCIe PHY
PCIe PHY
Open
Drain 3.3V
Open
Drain 3.3V
PCIe PHY
PCIe PHY
Open
Drain 3.3V
Open
Drain 3.3V
PCIe PHY
PCIe PHY
PCIe PHY
Open
Drain 3.3V
USB SS
PHY