Bt Interface - Quectel FG50V Hardware Design

The following figure shows the PCIe interface connection between FG50V and the host.
To ensure the signal integrity of PCIe interface, C1 and C2 should be placed close to the FG50V module, and C3
and C4 should be placed close to the host The extra stubs of traces must be avoided.
The following principles of PCIe interface design should be complied with, so as to meet PCIe Gen2 specifications.

It is important to route PCIE_TX_P/M, PCIE_RX_P/M, and PCIE_REFCLK_P/M as differential pairs with total
grounding. And the differential impedance should be 85 Ω ±10 %.
 The maximum trace length of each differential pair (PCIE_TX_P/M, PCIE_RX_P/M, and PCIE_REFCLK_P/M)
should be less than 300 mm, and trace length matching within each differential pair should be less than 0.7
mm.
 Space between PCIe signals and all other signals (inter-interface) should be four times the trace width.

Do not route signal traces under crystals, oscillators, magnetic devices, or RF signal traces. It is
important to route the PCIe differential traces in inner-layer of the PCB and surround the traces with
ground on that layer and with ground planes above and below.

3.6. BT Interface

The following figure shows the block diagram of BT interface connection between FG50V and the host.
FG50V_Hardware_Design
100K
100K
FG50V
PCIE_CLKREQ_N
PCIE_WAKE_N
PCIE_RST_N
R1 0R
PCIE_REFCLK_P
R2 0R
PCIE_REFCLK_M
100 nF
C1
PCIE_TX_P
100 nF
C2
PCIE_TX_M
100 nF
PCIE_RX_P
100 nF
PCIE_RX_M
Figure 5: PCIe Interface Connection
1V8
NM
Host
PCIE_CLKREQ
PCIE_WAKE
PCIE_RST
PCIE_REFCLK_P
PCIE_REFCLK_M
PCIE_RX0_P
PCIE_RX0_M
C3
PCIE_TX0_P
C4
PCIE_TX0_M
Wi-Fi&BT Module Series
FG50V Hardware Design
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