Power Supply - Quectel FG50V Hardware Design

BT_DBG_RXD
RF Antenna Interfaces
Pin Name
ANT_WIFI0
ANT_WIFI1
ANT_BT*
WLAN_SLP_CLK Interface
Pin Name
WLAN_SLP_CLK
RESERVED Interfaces
Pin Name
RESERVED
NOTE
"*" means under development.

3.4. Power Supply

The following table shows the power supply pins and ground pins of FG50V module.
FG50V_Hardware_Design
BT debug UART
22 DI
receive
Pin No. I/O Description
BT and WLAN
28 IO
antenna interface
WLAN antenna
33 IO
interface
Reserved
25 IO dedicated BT
antenna interface
Pin No. I/O Description
15 DI WLAN sleep clock
Pin No. I/O Description
4, 5, 8, 10, 17, 18, 40, 49, 50, 53, 55, 58, 62, 64, 68, 71–73, 79
Wi-Fi&BT Module Series
FG50V Hardware Design
V min = -0.3 V
IL
V max = 0.63 V
IL
V min = 1.17 V
IH
V max = 2.1 V
IH
DC Characteristics
DC Characteristics
V min = -0.3 V
IL
V max = 0.63 V
IL
V min = 1.17 V
IH
V max = 2.1 V
IH
DC Characteristics
Comment
50 Ω impedance.
50 Ω impedance.
50 Ω impedance.
Comment
1.8 V power domain.
If unused, keep this pin
open.
Comment
Keep these pins open.
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