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■ When [ExposureMode] is [Timed]
• Line Start Trigger : On
Shutter select mode
Next trigger start prohibited period
Trigger
Ｂ
EEN
Set Value + Offset(C)
LVAL
DVAL
• Common to [Binning Off] and [Vertical Binning On]
TapGeometry
Bit/Pixel
1X2
8/10
1X3
8
1X4
8/10
1X8
8/10
1X10
8
*) About CL Pixel Clock [MHz] and time of 1Clock.
CL Pixel Clock [MHz] : 31.70
CL Pixel Clock [MHz] : 42.41
CL Pixel Clock [MHz] : 63.39
CL Pixel Clock [MHz] : 84.82
//
A
D
//
//
CL Pixel
Line Period
Clock[MHz]
(CLK) [A]
31.70
4115
42.41
4129
63.39
4115
84.82
4130
31.70
2741
42.41
2750
63.39
2741
84.82
2751
31.70
2058
42.41
2065
63.39
2058
84.82
2065
31.70
1029
42.41
1033
63.39
1030
84.82
1033
31.70
823
42.41
826
63.39
823
84.82
849
1CLK : 0.0315μs
1CLK : 0.0236μs
1CLK : 0.0158μs
1CLK : 0.0118μs
Next trigger input allowed period
//
E
Delay time
Exposure
From Trigger
Offset Time
to EEN rising
(μs) [C]
(μs) [B]
1.1
-1.2
1.1
-1.2
1.1
-1.2
1.1
-1.2
1.1
-1.2
1.1
-1.2
1.1
-1.2
1.1
-1.2
1.1
-1.2
1.1
-1.2
1.1
-1.2
1.1
-1.2
1.1
-1.2
1.1
-1.2
1.1
-1.2
1.1
-1.2
1.1
-1.2
1.1
-1.2
1.1
-1.2
1.1
-1.2
— 25 —
SW-8000M-PMCL
//
F
//
Period From
EEN Falling
Data
to LVAL
invalid time
rising
(CLK) [E]
(μs) [D]
18.9
19
18.8
33
18.8
19
18.7
34
18.9
13
18.9
22
18.8
13
18.7
23
18.9
10
18.9
17
18.8
10
18.7
17
18.9
5
18.9
9
18.7
6
18.7
9
18.9
5
18.9
8
18.8
5
18.7
31
Data
valid time
(CLK) [F]
4096
4096
4096
4096
2728
2728
2728
2728
2048
2048
2048
2048
1024
1024
1024
1024
818
818
818
818
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