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SuperServer 6029TP-HTR/HC0R/HC1R User's Manual
Advanced Power Management Configuration
CPU P State Control
SpeedStep (PStates)
EIST (Enhanced Intel SpeedStep Technology) allows the system to automatically adjust
processor voltage and core frequency in an effort to reduce power consumption and heat
dissipation. Please refer to Intel's website for detailed information. The options are Disable
and Enable.
EIST PSD Function (Available when SpeedStep is set to Enable)
Use this feature to configure the processor's P-State coordination settings. During a P-State,
the voltage and frequency of the processor will be reduced when it is in operation. This
makes the processor more energy efficient, resulting in further energy gains. The options
are HW_ALL, SW_ALL and SW-ANY.
Turbo Mode (Available when SpeedStep is set to Enable)
Select Enable for processor cores to run faster than the frequency specified by the
manufacturer. The options are Disable and Enable.
Hardware PM (Power Management) State Control
Hardware P-States
If this feature is set to Disable, hardware will choose a P-state setting for the system based
on an OS request. If this feature is set to Native Mode, hardware will choose a P-state
setting based on OS guidance. If this feature is set to Native Mode with No Legacy Support,
hardware will choose a P-state setting independently without OS guidance. The options
are Disable, Native Mode, Out of Band Mode, and Native Mode with No Legacy Support.
CPU C State Control
Autonomous Core C-State
Select Enable to support Autonomous Core C-State control which will allow the processor
core to control its C-State setting automatically and independently. The options are Enable
and Disable.
CPU C6 Report
Select Enable to allow the BIOS to report the CPU C6 state (ACPI C3) to the operating
system. During the CPU C6 state, power to all caches is turned off. The options are Auto,
Enable, and Disable.
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Enhanced Halt State (C1E)
Select Enable to enable "Enhanced Halt State" support, which will significantly reduce the
CPU's power consumption by minimizing CPU's clock cycles and reduce voltage during a
"Halt State." The options are Disable and Enable.
Package C State Control
Package C State
Use this feature to set the limit on the C-State package register. The options are C0/1 state,
C2 state, C6 (non-Retention) state, C6 (Retention) state, No Limit, and Auto.
CPU T State Control
Software Controlled T-States
If this feature is set to Enable, CPU throttling settings will be supported by the software of
the system. The options are Disable and Enable.
Chipset Configuration
Warning: Setting the wrong values in the following sections may cause the system to malfunc-
tion.
North Bridge
This feature allows the user to configure the settings for the Intel North Bridge.
UPI (Ultra Path Interconnect) Configuration
This section displays the following UPI General Configuration information:
•
Number of CPU
•
Number of IIO
•
Current UPI Link Speed
•
Current UPI Link Frequency
•
UPI Global MMIO Low Base/Limit
•
UPI Global MMIO High Base/Limit
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Chapter 4: BIOS
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