Sleep Mode; Suspend Mode - Toshiba TXZ+ Series Reference Manual

Sleep Mode

Sleep mode is requested by a write of "1" to the [CANxMCR]<SMR> bit. After the CAN controller has entered
into sleep mode, the [CANxGSR]<SMA> bit is set to "1".
The read value of the [CANxGSR] register is "0x0001F040". This means that there is no message in the
transmission buffer and sleep mode is active where the <SMA> bit is "1". Read values to all other registers deliver
the value "0". Write accesses to all registers, except the [CANxMCR] register, will be denied.
The CAN controller cancels sleep mode (wakes up) and starts the power-up sequence if a write access to the
[CANxMCR] register is detected, or there is any bus activity detected on the CAN bus with the
[CANxMCR]<WUBA> bit set to "1". The CAN controller waits until detecting 11 consecutive recessive bits on
the CANxRX input terminal, after it goes into bus active state. The wake-up message is invalid.
In sleep mode, the CAN error counters and all transmission request set [CANxTRS]<TRSn> bits and transmission
request reset [CANxTRR]<TRRn> bits are cleared. The [CANxMCR]<SMR> bit and the [CANxGSR]<SMA> bit
are cleared after the CAN controller leaves sleep mode.
If sleep mode is requested while the CAN controller is transmitting a message ([CANxMCR]<SMR>=1), the CAN
controller enters sleep mode after any of the following occurs:
● The message has been successfully transmitted.
●
The message has been successfully transmitted after an arbitration lost error.
●
The message has been successfully received after an arbitration lost error.

Suspend Mode

The suspend mode is requested by writing "1" to the [CANxMCR]<SUR> bit. If the CAN bus line is not idle, the
current message transmission/reception is completed before suspend mode is activated. After the CAN controller
has entered suspend mode, the [CANxGSR]<SUA> bit is set to "1".
In suspend mode, the CAN controller is not active on the CAN bus line. That means neither error frames nor
acknowledgment will be sent. The error counters and the [CANxGSR]<EP> bit will not be cleared either.
If suspend mode is requested during the bus off recovery sequence execution, the CAN controller enters suspend
mode after the bus off recovery sequence is finished.
To restart the CAN controller, the [CANxMCR]<SUR> bit needs to be programmed to "0". After leaving the bus
off state or the inactive state, the CAN controller restarts the bus off recovery sequence.
The CAN controller cancels suspend mode with a write of "0" to the [CANxMCR]<SUR> bit.
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TXZ+ Family
CAN Controller
2020-10-01
Rev. 1.0