Time Stamp Function; Figure 3.4 Timer Stamp Counter - Toshiba TXZ+ Series Reference Manual

Time Stamp Function

There is a free-running 16-bit time stamp counter [CANxTSC] implemented in the CAN controller to show the
time of message reception and transmission. The content of the [CANxTSC] is written into the time stamp value
(TSV) of the corresponding mailbox when a received message has been stored or a message has been transmitted.
The [CANxTSC] is driven by the bit clock of the CAN bus line. When the operation mode of the CAN is in
configuration mode or in sleep mode, the [CANxTSC] is stopped. After power-up reset, a write to the time stamp
counter prescaler register [CANxTSP] clears the [CANxTSC] to "0". The [CANxTSC] is readable and writable
from the CPU both in configuration mode and normal operation mode.
Figure 3.4 shows the structure of the time stamp counter.
MCU read/write
CAN bus bit clock
MCU read/write
Transmission/Reception
successful
The free running time stamp counter and the time stamp hold register will be cleared in the following cases:
●
After reset (Power on reset or software reset).
●
When the controller enters into configuration mode.
●
When the controller enters into sleep mode.
●
When a write access is performed to the
Prescaler Register
<TSP[3:0]>
Re-load value
Prescaler (4 bit)
Count-up clock
Free running
Time Stamp Counter
<TSC[15:0]>
load
Time Stamp Hold Register
(16 bit)
MailBox RAM

Figure 3.4 Timer Stamp Counter

[CANxTSP]
re-load
clear
clear
clear
register.
17 / 52
TXZ+ Family
CAN Controller
Entering sleep mode
Entering configuration mode
Write to prescaler
Hardware/Software reset
Hardware/Software reset
Entering sleep mode
Entering configuration mode
Write to prescaler
2020-10-01
Rev. 1.0