Toshiba TXZ+ Series Reference Manual
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Toshiba TXZ+ Series Reference Manual

32-bit risc microcontroller, clock control and operation mode cg-m4g(1)-c
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TXZ+ Family
TMPM4G Group(1)
Clock Control and Operation Mode
32-bit RISC microcontroller
TXZ+ Family
TMPM4G Group(1)
Reference Manual
Clock Control and Operation Mode
(CG-M4G(1)-C)
Revision 1.1
2021-06
2021-06-30
1 / 88
© 2020-2021
Rev. 1.1
Toshiba Electronic Devices & Storage Corporation

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  • Page 1 TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode 32-bit RISC microcontroller TXZ+ Family TMPM4G Group(1) Reference Manual Clock Control and Operation Mode (CG-M4G(1)-C) Revision 1.1 2021-06 2021-06-30 1 / 88 © 2020-2021 Rev. 1.1 Toshiba Electronic Devices & Storage Corporation...

  • Page 2: Table Of Contents

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Contents Preface ................................. 7 Related document ..............................7 Conventions ................................8 Terms and Abbreviations ............................10 Clock Control and Operation Mode ......................11 Outlines ................................11 Clock control ..............................11 Clock type ................................... 11 The initial value by a reset action ..........................
  • Page 3 TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode NORMAL → STOP2 → RESET → NORMAL Operation mode transition ..............35 Explanation of a register ..........................36 Register list ................................. 36 Detail of Register ................................ 37 [CGPROTECT] (CG write protection register) ....................... 37 [CGOSCCR] (Oscillation control register) ........................
  • Page 4 TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Cold reset ................................... 74 Reset by a Power On Reset Circuit (without using a RESET_N pin) ................75 Reset by a RESET_N pin .............................. 76 Reset extension by LVD ..............................78 Warm reset .................................
  • Page 5 TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode List of Figure Figure 1.1 Clock system diagram......................13 Figure 1.2 Change state ........................... 28 Figure 1.3 STOP2 mode restart operation flow ..................33 Figure 1.4 NORMAL → STOP1 → NORMAL Operation mode transition ..........34 Figure 1.5 NORMAL →...
  • Page 6 TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode List of Tables Table 1.1 Details of a [CGPLL0SEL] <PLL0SET [23:0]>setup..............16 Table 1.2 PLL correction (example) ......................17 Table 1.3 PLL0SET setting value (example) ................... 17 Table 1.4 Clock domains of CPU and peripherals ................... 19 Table 1.5 Time interval for changing System clock .................

  • Page 7: Preface

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Preface Related document Document name Documentation of Cortex ® ® Exception Input/Output Ports Voltage Detection Circuit Selective Clock Watch Dog Timer Flash Memory Datasheet of Products (Electrical Characteristics) 2021-06-30 7 / 88 Rev.

  • Page 8: Conventions

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Conventions ● Numeric formats follow the rules as shown below: Hexadecimal: 0xABC Decimal: 123 or 0d123 - Only when it needs to be explicitly shown that they are decimal numbers. Binary: 0b111 - It is possible to omit the “0b” when the number of bit can be distinctly understood from a sentence.
  • Page 9 TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode *********************************************************************************************************************** Arm, Cortex and Thumb are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All rights reserved. *********************************************************************************************************************** All other company names, product names, and service names mentioned herein may be trademarks of their respective companies.

  • Page 10: Terms And Abbreviations

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Terms and Abbreviations Some of abbreviations used in this document are as follows: Analog to Digital Converter A-PMD Advanced Programmable Motor Control Circuit Clock control and Generations Consumer Electronics Control Digital to Analog Converter Digital Noise Filter EBIF External Bus Interface...

  • Page 11: Clock Control And Operation Mode

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode 1. Clock Control and Operation Mode Outlines The clock/mode control block can select a clock gear and prescaler clock, and set the warming-up of oscillator and so on. Furthermore, it has Normal mode and a low power consumption mode in order to reduce power consumption using mode transition.

  • Page 12: The Initial Value By A Reset Action

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode The initial value by a reset action A clock setup is initialized to the following states by a reset action. External high speed oscillator : Stop Internal high speed oscillator 1 : Oscillation Internal high speed oscillator 2 : Stop (Note)

  • Page 13: Clock System Diagram

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Clock System diagram The figure below shows a clock system diagram. [CGSPCLKEN] <ADCKEN> ADCLK Source clock control [CGWUPHCR]<WUON> [CGWUPHCR]<WUPT[15:4]> High speed Warming up timer [CGFCEN] fsysh <FCIPENx> [CGWUPHCR] （Middle speed system clock） <WUCLK>...

  • Page 14: Warming Up Function

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Warming up function A warming up function starts the warming up timer for high speed oscillator automatically to secure the oscillation stable time when the STOP1 mode is released. It is also available as a count-up timer which uses the warming up timer for high speed oscillator to secure the stability of an external oscillator or an internal oscillator.

  • Page 15: The Warming Up Timer For A Low Speed Oscillation

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode The warming up timer for a low speed oscillation A 19-bit up-counter is built in as a warming up timer only for a low speed oscillation. Calculate with the following formula and set [CGWUPHCR]<WUPT[18:4]> to the upper 15 bits of the result. Lower 4bits are ignored. 16 is subtracted in order to perform the count for lower 4bits, even when a set point is 0x0000.

  • Page 16: Clock Multiplying Circuit (Pll) For Fsys

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Clock multiplying circuit (PLL) for fsys The clock multiplying circuit outputs the f clock (maximum 200MHz) multiplied by the optimum condition for the frequency (8 MHz to 24 MHz) of the output clock f of the high speed oscillator.

  • Page 17: Change Of The Pll Multiplication Value Under Operation

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode ≤ Maximum Operating Frequency Note2: There is no Linearity in the frequency by the Fractional part Multiplication setup. Note3: f Table 1.2 PLL correction (example) (MHz) <PLL0SET [23:17] > (a decimal, an integral value) 8.00 10.00 12.00...

  • Page 18: Pll Operation Start / Stop / Switching Procedure

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode PLL operation start / stop / switching procedure (1) fc setup (PLL stop → PLL start) As an fc setup, the example of switching procedure from the PLL stop state to the PLL operation state is as follows.

  • Page 19: System Clock

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode System clock An internal high speed oscillation clock or external high speed oscillation clock (connected oscillator or clock input) can be used as a source of system clock. The system clock consists of “High speed system clock (f )(maximum 200MHz )”...

  • Page 20: The Setting Method Of A System Clock

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Table 1.6 shows the example of operating frequency by the clock gear ratio (1/1 to 1/16) to the frequency fc set up with Oscillation frequency, a PLL multiplication value, etc. Table 1.6 Example of operating frequency Operating frequency (MHz) by Operating frequency (MHz) External...
  • Page 21 TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode (2) fosc setup (Internal oscillation → External clock input) As a f setup, the example of switching procedure to the external clock input (EHCLKIN) from an internal oscillation 1(IHOSC1) is shown below. <<...

  • Page 22: Low Speed Clock

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Low speed clock ELOSC Setting (No Operation of External Low Speed Oscillator → Operation) An example of setting procedure is shown as follows to use the external low speed oscillator (ELOSC). <<...

  • Page 23: Clock Supply Setting Function

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Clock supply setting function This MCU has the clock on/off function for the peripheral circuits. To reduce the power consumption, this MCU can stop supplying the clock to the peripheral functions that are not used. Except some peripheral functions, clocks are not supplied after reset.

  • Page 24: Operation Mode

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Operation mode There are NORMAL mode and a Low Power consumption mode (IDLE, STOP1, STOP2) in this product as an Operation mode, and it can reduce power consumption by performing mode changes according to directions for use.

  • Page 25: Transition To And Return From Low Power Consumption Mode

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode This product will be cut off the power except for the following circuit in STOP2 mode. ▪ External low speed oscillator (ELOSC) ▪ ▪ Backup RAM ▪ Port pin status ▪ ▪...

  • Page 26: The Peripheral Function State In A Low Power Consumption Mode

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode The peripheral function state in a Low Power Consumption mode The following Table 1.10 shows the Operation State of the peripheral function (block) in each mode. In addition, after reset release, it will be in the state where a clock is not supplied except for some blocks. If needed, set up [CGFSYSENA], [CGFSYSMENA], [CGFSYSMENB], [CGFCEN], [CGSPCLKEN] and enable clock supply.
  • Page 27 TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Note3: A port state when the [RLMSHTDNOP] <PTKEEP> is set to "1" is held. Note4: This operation is enabled by setting LTTMR as a sampling clock. Note5: This function is enabled when [RLMLOSCCR]<POSCEN> is set to “1”. Note6: It becomes a data hold when peripheral functions (DMA etc.) which carry out data access (R/W), except CPU, are not connected on the bus matrix.

  • Page 28: Switch To And Return From A Low Power Consumption Mode

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Switch to and return from a Low Power Consumption mode Reset Reset (Cut off internal power supply After reset, the high speed block) oscillator1(IHOSC1) oscillates. (Note2) Interrupt (Note2) Interrupt Interrupt STOP2 Mode NORMAL STOP1 Mode Mode...

  • Page 29: Stop1 Mode Transition Flow

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode STOP1 mode transition flow Set up the following procedure at switching to STOP1. Because STOP1 mode is released by an interrupt, set the interrupt before switching to STOP1 mode. For the interrupts that can be used to release the STOP1 mode, refer to "1.3.3.1The release source of a Low Power Consumption mode".

  • Page 30: Stop2 Mode Transition Flow

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode STOP2 mode transition flow Set up the following procedure at switching to STOP2. Because STOP2 mode is released by an interrupt, set the interrupt before switching to STOP2 mode. For the interrupts that can be used to release the STOP2 mode, refer to "1.3.3.1The release source of a Low Power Consumption mode".

  • Page 31: Return From A Low Power Consumption Mode

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Return from a Low Power Consumption mode The release source of a Low Power Consumption mode Interrupt, Non-Maskable Interrupt, and reset can perform release from a Low Power Consumption mode. The standby release source which can be used is decided by a Low Power Consumption mode.

  • Page 32: Warming Up At The Release Of Low Power Consumption Mode

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode ● Released by an interrupt request When interrupt cancels a Low Power Consumption mode, it is necessary to prepare so that interrupt may be detected by CPU. The interrupt used for release in STOP1 and STOP2 modes needs to set up CPU, and needs to set up detection by INTIF.

  • Page 33: Restart Operation From Stop2 Mode

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Restart operation from STOP2 mode The restart operation flow from STOP2 mode release factor interrupt generating is as follows. Release factor generating Check reset flag (Note1) • [RLMRSTFLGx]=xx (it is checked by which factor reset has occurred) STOP2 release interrupt RESET_N pin or LVD reset...

  • Page 34: Clock Operation By Mode Transition

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Clock operation by mode transition The clock operation in case of mode transition is shown below. NORMAL → IDLE → NORMAL Operation mode transition CPU stops at IDLE mode. The clock supply to a peripheral function holds a setting state. Please perform operation/stop by the register of each peripheral function, a clock supply setting function, etc.

  • Page 35: Normal → Stop2 → Reset → Normal Operation Mode Transition

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode NORMAL → STOP2 → RESET → NORMAL Operation mode transition Warming up is not performed when returning to NORMAL mode by any reset. Even when returning to NORMAL mode except for RESET, it branches to the interrupt routine of reset. A reset operation is performed to an internal main power domain after STOP2 mode released.

  • Page 36: Explanation Of A Register

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Explanation of a register Register list The register related to CG and its address information are shown below. Peripheral function Channel/Unit Base address Clock Control and 0x40083000 Operation Mode Low speed oscillation/ 0x4003E400 power control Clock Control and Operation Mode...

  • Page 37: Detail Of Register

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Detail of Register [CGPROTECT] (CG write protection register) After Bit Symbol Type Function reset 31:8 Read as “0”. Control write-protection for the CG register (all registers except for this register) PROTECT[7:0] 0xC1 0xC1: CG Registers are write-enabled (Protect disable).

  • Page 38: [Cgsyscr] (System Clock Control Register)

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode [CGSYSCR] (System clock control register) After Bit Symbol Type Function reset Middle speed prescaler clock (ΦT0m) selection status 00: <PRCK[3:0]> setting value (no division) 31:30 MCKSELPST[1:0] 01: <PRCK[3:0]> setting value is divided by 2 1*: <PRCK[3:0]>...

  • Page 39: [Cgstbycr] (Standby Control Register)

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode [CGSTBYCR] (Standby control register) After Bit Symbol Type Function reset 31:2 Read as "0". Selects a low power consumption mode. 00: IDLE STBY[1:0] 01: STOP1 10: STOP2 11: Reserved [CGPLL0SEL] (PLL selection register for fsys) After Bit Symbol Type...

  • Page 40: [Cgwuphcr] (High Speed Oscillation Warming Up Register)

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode [CGWUPHCR] (High speed oscillation warming up register) After Bit Symbol Type Function reset Sets the upper 12 bits of the 16 bits of calculation values of the warming up timer. 31:20 WUPT[15:4] 0x800 About a setup of a warming up timer, refer to the “1.2.4.1The...

  • Page 41: [Cgfsysmenc] (Middle Speed Clock Supply And Stop Register C For Fsysm)

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode [CGFSYSMENC] (Middle speed clock supply and stop register C for fsysm) After Bit Symbol Type Function reset 31:17 Read as “0” Clock enable of T32A ch15 IPMENC16 0: Clock stop 1: Clock supply Clock enable of T32A ch14 IPMENC15 0: Clock stop...

  • Page 42: [Cgfsysmena] (Middle Speed Clock Supply And Stop Register A For Fsysm)

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode [CGFSYSMENA] (Middle speed clock supply and stop register A for fsysm) After Bit Symbol Type Function reset Clock enable of I2C ch2 IPMENA31 0: Clock stop 1: Clock supply Clock enable of I2C ch1 IPMENA30 0: Clock stop 1: Clock supply...
  • Page 43 TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode After Bit Symbol Type Function reset Clock enable of T32A ch04 IPMENA10 0: Clock stop 1: Clock supply Clock enable of T32A ch03 IPMENA09 0: Clock stop 1: Clock supply Clock enable of T32A ch02 IPMENA08 0: Clock stop 1: Clock supply...

  • Page 44: [Cgfsysmenb] (Middle Speed Clock Supply And Stop Register B For Fsysm)

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode [CGFSYSMENB] (Middle speed clock supply and stop register B for fsysm) After Bit Symbol Type Function reset Clock enable of SIWDT IPMENB31 0: Clock stop 1: Clock supply Clock enable of NBDIF IPMENB30 0: Clock stop 1: Clock supply...
  • Page 45 TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode After Bit Symbol Type Function reset Clock enable of PORT F IPMENB07 0: Clock stop 1: Clock supply Clock enable of PORT E IPMENB06 0: Clock stop 1: Clock supply Clock enable of PORT D IPMENB05 0: Clock stop 1: Clock supply...

  • Page 46: [Cgfsysena] (High Speed Clock Supply And Stop Register A For Fsysh)

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode [CGFSYSENA] (High speed clock supply and stop register A for fsysh) After Bit Symbol Type Function reset 31:10 Read as “0” Clock enable of TSPI ch5 IPENA09 0: Clock stop 1: Clock supply Clock enable of TSPI ch4 IPENA08 0: Clock stop...

  • Page 47: [Cgfcen] (Clock Supply And Stop Register For Fc)

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode [CGFCEN] (Clock supply and stop register for fc) After Bit Symbol Type Function reset 31:28 Read as “0” Clock enable of DNF Unit B FCIPEN27 0: Clock stop 1: Clock supply Clock enable of DNF Unit A FCIPEN26 0: Clock stop...

  • Page 48: [Cgextend2] (Function Extension Register 2)

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode [CGEXTEND2] (Function extension register 2) After Bit Symbol Type Function reset 31:3 Read as "0". MDMAC software reset It is generated with the continuous writes of “0”, “1” and “0” in order.

  • Page 49: [Rlmshtdnop](Power Supply Cut Off Control Register)

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode [RLMSHTDNOP](Power supply cut off control register) After Bit Symbol Type Function reset Write "0". Read as "0". The I/O control signal in the STOP2 mode is held. 0: Control by Port PTKEEP 1: Hold the state when it changes into 1 from 0 A setup is required before the STOP2 mode transition.

  • Page 50: Information According To Product

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Information according to product The information about [CGFSYSENA], [CGFSYSMENA], [CGFSYSMENB], [CGFSYSMENC] and [CGFCEN] which is different according to each product is shown below. [CGFSYSENA] Table 1.13 [CGFSYSENA] register corresponding to each product Internal connection Channel No./ Bit Symbol...

  • Page 51: [Cgfsysmena]

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode [CGFSYSMENA] Table 1.14 [CGFSYSMENA] register corresponding to each product Internal connection Channel No./ Bit Symbol M4GR M4GQ M4GN peripheral circuit Port name IPMENA31    IPMENA30    IPMENA29 ...

  • Page 52: [Cgfsysenb]

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode [CGFSYSENB] Table 1.15 [CGFSYSMENB] register corresponding to each product Internal connection Channel No./ Bit Symbol M4GR M4GQ M4GN peripheral circuit Port name IPMENB31 SIWDT    IPMENB30 NBDIF   ...

  • Page 53: [Cgfsysenc]

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode [CGFSYSENC] Table 1.16 [CGFSYSMENC] register corresponding to each product Internal connection Channel No./ Bit Symbol M4GR M4GQ M4GN peripheral circuit Port name IPMENC31 IPMENC30 IPMENC29 IPMENC28 IPMENC27 IPMENC26 IPMENC25 IPMENC24 IPMENC23 IPMENC22 IPMENC21 IPMENC20...

  • Page 54: [Cgfcen]

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode [CGFCEN] Table 1.17 [CGFCEN] register corresponding to each product Internal connection Channel No./ Bit Symbol M4GR M4GQ M4GN peripheral circuit Port name FCIPEN31 FCIPEN30 FCIPEN29 FCIPEN28 FCIPEN27    FCIPEN26 ...

  • Page 55: Memory Map

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode 2. Memory Map Outline The memory maps for TMPM4G group (1) are based on the Arm Cortex-M4(with FPU) processor core memory map. The internal ROM, internal RAM and special function registers (SFR) are mapped to the Code, SRAM and peripheral regions of the Cortex-M4(with FPU) respectively.

  • Page 56: Tmpm4Gxf20

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode TMPM4GxF20 - Code Flash 2048KB - RAM 256KB+2KB(Backup RAM) - Data Flash 32KB - Products TMPM4GRF20FG, TMPM4GRF20XBG, TMPM4GQF20FG, TMPM4GQF20XBG, TMPM4GNF20FG 0xFFFFFFFF 0xFFFFFFFF Vendor-Specific Vendor-Specific 0xE0100000 0xE0100000 CPU Register Region CPU Register Region 0xE0000000 0xE0000000 Fault...

  • Page 57: Tmpm4Gxf15

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode TMPM4GxF15 - Code Flash 1536KB - RAM 256KB+2KB(Backup RAM) - Data Flash 32KB - Products TMPM4GRF15FG, TMPM4GRF15XBG, TMPM4GQF15FG, TMPM4GQF15XBG, TMPM4GNF15FG 0xFFFFFFFF 0xFFFFFFFF Vendor-Specific Vendor-Specific 0xE0100000 0xE0100000 CPU Register Region CPU Register Region 0xE0000000 0xE0000000 Fault...

  • Page 58: Tmpm4Gxf10

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode TMPM4GxF10 - Code Flash 1024KB - RAM 256KB+2KB(Backup RAM) - Data Flash 32KB - Products TMPM4GRF10FG, TMPM4GRF10XBG, TMPM4GQF10FG, TMPM4GQF10XBG, TMPM4GNF10FG 0xFFFFFFFF 0xFFFFFFFF Vendor-Specific Vendor-Specific 0xE0100000 0xE0100000 CPU Register Region CPU Register Region 0xE0000000 0xE0000000 Fault...

  • Page 59: Tmpm4Gxfd

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode TMPM4GxFD - Code Flash 512KB - RAM 192KB+2KB(Backup RAM) - Data Flash 32KB - Products TMPM4GRFDFG, TMPM4GRFDXBG, TMPM4GQFDFG, TMPM4GQFDXBG, TMPM4GNFDFG 0xFFFFFFFF 0xFFFFFFFF Vendor-Specific Vendor-Specific 0xE0100000 0xE0100000 CPU Register Region CPU Register Region 0xE0000000 0xE0000000 Fault...

  • Page 60: Bus Matrix

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Bus Matrix This microcontroller consists of CPU core of the main master, High-speed DMA controller (HDMAC), and a sub-master. The sub-master consists of Multi-function DMA controller (MDMAC) and NBDIF. The signals of the main master are connected to the slave ports (S0 to S5) of the bus matrix. In the bus matrix, the signals of the slave ports are selectively connected to the master ports (M0 to M15).

  • Page 61: Structure

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Structure Single chip mode High speed clock domain NBDIF Middle speed clock domain Cortex-M4 HDMAC HDMAC UnitA UnitB with FPU SyncUp Instruction Code Flash Data System Data Flash BootROM RAM0 TSPI(SFR) RAM1 EBIF(SFR) TRGSEL...

  • Page 62: Single Boot Mode

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Single boot mode High speed clock domain Middle speed clock domain NBDIF Cortex-M4 HDMAC HDMAC UnitA UnitB with FPU SyncUp Instruction Code Flash Data System Data Flash BootROM RAM0 TSPI(SFR) RAM1 EBIF(SFR) TRGSEL RAM2...

  • Page 63: Connection Table

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Connection table Code area / SRAM area / SMIF area / External bus area (1) TMPM4GxF20 ● Single chip mode Table 2.1 TMPM4GxF20 Single chip mode Sub master Main master MDMAC HDMAC HDMAC Core...

  • Page 64: Table 2.2 Tmpm4Gxf20 Single Boot Mode

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode ● Single boot mode Table 2.2 TMPM4GxF20 Single boot mode Sub master Main master MDMAC HDMAC HDMAC Core Core Core Start Address Slave NBDIF unit A unit A unit B S-Bus D-Bus I-Bus 0x00000000...

  • Page 65: Table 2.3 Tmpm4Gxf15 Single Chip Mode

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode (2) TMPM4GxF15 ● Single chip mode Table 2.3 TMPM4GxF15 Single chip mode Sub master Main master Start MDMAC HDMAC HDMAC Core Core Core Slave NBDIF Address unit A unit A unit B S-Bus D-Bus I-Bus...

  • Page 66: Table 2.4 Tmpm4Gxf15 Single Boot Mode

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode ● Single boot mode Table 2.4 TMPM4GxF15 Single boot mode Sub master Main master Start MDMAC HDMAC HDMAC Core Core Core Slave NBDIF Address unit A unit A unit B S-Bus D-Bus I-Bus 0x00000000...

  • Page 67: Table 2.5 Tmpm4Gxf10 Single Chip Mode

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode (3) TMPM4GxF10 ● Single chip mode Table 2.5 TMPM4GxF10 Single chip mode Sub master Main master MDMAC HDMAC HDMAC Core Core Core Start Address Slave NBDIF unit A unit A unit B S-Bus D-Bus I-Bus...

  • Page 68: Table 2.6 Tmpm4Gxf10 Single Boot Mode

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode ● Single boot mode Table 2.6 TMPM4GxF10 Single boot mode Sub master Main master Start MDMAC HDMAC HDMAC Core Core Core Slave NBDIF Address unit A unit A unit B S-Bus D-Bus I-Bus 0x00000000...

  • Page 69: Table 2.7 Tmpm4Gxfd Single Chip Mode

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode (4) TMPM4GxFD ● Single chip mode Table 2.7 TMPM4GxFD Single chip mode Sub master Main master MDMAC HDMAC HDMAC Core Core Core Start Address Slave NBDIF unit A unit A unit B S-Bus D-Bus I-Bus...

  • Page 70: Table 2.8 Tmpm4Gxfd Single Boot Mode

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode ● Single boot mode Table 2.8 TMPM4GxFD Single boot mode Sub master Main master MDMAC HDMAC HDMAC Core Core Core Start Address Slave NBDIF unit A unit A unit B S-Bus D-Bus I-Bus 0x00000000...

  • Page 71: Peripheral Area

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Peripheral Area Table 2.9 Peripheral Area Sub master Main master MDMAC HDMAC HDMAC Core Core Core Start Address Slave NBDIF unit A unit A unit B S-Bus D-Bus I-Bus 0x40000000 HDMAC(unit A) Fault Fault ...

  • Page 72: Ram Access

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode RAM Access The number of clocks required to access the internal RAM is shown in the table below. Table 2.10 The number of clocks to access each RAM fsys Clock description RAM0 fsysh RAM1...
  • Page 73 TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode [FCRACCR] (RAM Access Control Register) Bit Symbol After reset Type Function 31:14 Read as “0” 13:12 Write as “00” 11:10 Read as “0” Write as “00” Read as “0” Access control to RAM1, RAM2 00: 1clock (fsysh ≤...

  • Page 74: Reset And Power Control

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode 3. Reset and Power Control Outline Function classification Factor Functional Description Reset which occurs at the time of a power supply Power On Reset turning on or turning off. LVD reset Reset which occurs below the set-up voltage Cold reset (Reset with power on)

  • Page 75: Reset By A Power On Reset Circuit (Without Using A Reset_N Pin)

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Reset by a Power On Reset Circuit (without using a RESET_N pin) After a supply voltage exceeds the release voltage of a Power On Reset (POR), internal reset is deasserted after "Internal initialization time"...

  • Page 76: Reset By A Reset_N Pin

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Reset by a RESET_N pin When turn on a power supply, it can control the timing of reset release by using RESET_N pin. After a supply voltage exceeds the release voltage of a Power On Reset and even after "Internal initialization time" elapsed, if the RESET_N pin is "Low", internal reset continues.

  • Page 77: Figure 3.3 Reset Operation By A Reset_N Pin (2)

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode In case of RESET_N pin input change from "Low" to "High" before "Internal initialization time" elapses, internal reset signal is released after "Internal initialization time" elapses. Please goes up a supply voltage into an operating voltage range before "Internal initialization time" elapses. The CPU operates after internal reset release.

  • Page 78: Reset Extension By Lvd

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Reset extension by LVD When the power supply voltage has not exceeded the LVD release voltage even after "Internal initialization time" elapsed, LVD generates the reset signal and the reset state continues. After the power supply voltage exceeds the LVD release voltage and "LVD detection release time"...

  • Page 79: Warm Reset

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Warm reset Warm reset by REST_N pin When resetting with the RESET_N pin, set the RESET_N pin to "Low" at 17.2 μs or more while the power supply voltage is within the operating range. When the "Low"...

  • Page 80: Reset By Stop2 Mode Release

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Reset by STOP2 mode release When RESET_N pin changed "Low" or LVD reset occurred during STOP2 mode, STOP2 released. The power supply is turned on and assert reset to Main Power Domain. After RESET_N pin changes to "High" or LVD reset released, start operate in NORMAL mode.

  • Page 81: Start Up By Power On Reset (Not Using Reset_N Pin Signal)

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Start up by Power On Reset (Not Using RESET_N Pin Signal) "Low" should be input to BOOT_N pin after the power is supplied. And after the internal reset is deasserted and the CPU operation starts, the single boot mode starts up.

  • Page 82: Starting In The Single Boot Mode When Power Supply Is Stable

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Starting in the single boot mode when power supply is stable When the supply voltage is stable within an operating voltage range, input "Low" to RESET_N pin for reset longer than "Internal processing time", while "Low" is inputted to the BOOT_N pin. And deassert RESET_N pin to "High".

  • Page 83: Power On Reset Circuit

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Power On Reset Circuit The Power On Reset Circuit (POR) generates a reset signal when the power is turned on or turned off. Note: The Power On Reset Circuit may not operate correctly due to the fluctuation of the power supply. Equipment should be designed with full consideration of the electrical characteristics.

  • Page 84: Precautions When Turning Off The Power

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode Precautions when turning off the power When turning off the power, always follow the prescribed procedure to reduce the power supply voltage. DVDD3= DVDD3A= DVDD3B= DVDD3C= DVDD3D= DVDD3E= DVDD3F= DVDD3G= DVDD3H= AVDD3 Power off falling gradient Operation Voltage...

  • Page 85: About Turn On Power Supply After Turn Off

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode About turn on power supply after turn off (1) When using external reset circuit or internal LVD reset output When the power supply is turned off and the power supply voltage drops below the operation guaranteed voltage, reset is performed with an external reset circuit or built-in LVD (when the voltage is less than the set voltage).

  • Page 86: A Reset Factor And The Reset Range

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode A reset factor and the reset range Reset factors and the range initialized are shown in Table 3.1. Table 3.1 A reset factor and the range initialized Reset factors STOP2 mode release Cold Reset Warm reset (Note1) Registers and Reset...

  • Page 87: Revision History

    TXZ+ Family TMPM4G Group(1) Clock Control and Operation Mode 4. Revision history Table 4.1 Revision history Revision Date Description 2020-12-14 First release - Correct Figure 1.3. - 1.3.3.3. The restart operation from the STOP2 mode Change Note2 to Note3, and Note3 is corrected. Added Note2.

  • Page 88: Restrictions On Product Use

    Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application with which the Product will be used with or for.

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