[Canxmbtif](Mailbox Transmit Interrupt Flag Register); [Canxmbrif](Mailbox Receive Interrupt Flag Register); [Canxmbim](Mailbox Interrupt Mask Register) - Toshiba TXZ+ Series Reference Manual

[CANxMBTIF](Mailbox Transmit Interrupt Flag Register)

Bit Bit Symbol After Reset Type
31 - 0
30:0 MBTIF[30:0] 0
When the mailbox is set to receive, the corresponding bit in the [CANxMBTIF] register is read as "0". When the
mailbox is set to transmit, the corresponding bit in the [CANxMBRIF] register is read as "0".

[CANxMBRIF](Mailbox Receive Interrupt Flag Register)

Bit Bit Symbol After Reset Type
31:0 MBRIF[31:0]

[CANxMBIM](Mailbox Interrupt Mask Register)

Bit Bit Symbol After Reset Type
31:0 MBIM[31:0]
The settings in [CANxMBIM] determine, for which mailbox the interrupt generation is enabled or disabled.
If a bit in [CANxMBIM] is "0", the interrupt generation for the corresponding mailbox is disabled and if it is "1",
the interrupt generation is enabled. Reset value of [CANxMBIM] is "0".
R Read as "0".
Mailbox transmission interrupt flag (Each bit corresponds to mailboxes 30 to 0.)
When the message in mailbox n has been successfully transmitted and the interrupt mask
of the [CANxMBIM] register is enabled (<MBIMn>=1), the <MBTIFn> bit is set to "1" and
the transmission completion interrupt (INTCANxTXD) becomes the "High" level.
When [CANxMBIM]<MBIMn> bit is "0", the <MBTIFn> bit is not set and INTCANxTXD
R/W
stays at the "Low" level.
Transmission completion is checked by reading the [CANxTA] register.
If even one bit in the [CANxMBTIF] register is "1", INTCANxTXD is the "High" level.
The <MBTIFn> bit is cleared by a write of "1" to the <MBTIFn> bit from the CPU.
A write of "0" is invalid.
Mailbox receive interrupt flag (Each bit corresponds to mailboxes 31 to 0.)
When mailbox n has successfully received the message and the interrupt mask of the
[CANxMBIM] register is enabled (<MBIMn> = 1). When the <MBIMn> bit in the, [CANxMBIM]
register is "0", the <MBRIFn> bit is not set and INTCANxRXD stays at the "Low" level. Receive
0 R/W
completion is checked by reading the [CANxRMP] register.
If even one bit in the [CANxMBRIF] register is "1", INTCANxRXD is the "High" level.
The <MBRIFn> bit is cleared by a write of "1" to the <MBRIFn> bit from the CPU.
A write of "0" is invalid.
Mailbox interrupt mask
0 R/W 0: Interrupt disabled for corresponding mailbox
1: Interrupt enabled for corresponding mailbox
Function
Function
Function
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TXZ+ Family
CAN Controller
2020-10-01
Rev. 1.0