[Canxcec](Canx Error Counter Register) - Toshiba TXZ+ Series Reference Manual

[CANxCEC](CANx Error Counter Register)

Bit Bit Symbol After Reset Type
31:16 - 0
0
15:8 TEC[7:0]
-
0
7:0 REC[7:0]
-
The CAN controller contains two error counters: the reception error counter <REC[7:0]> and the transmission
error counter <TEC[7:0]>. The value of both counters can be read from the CPU. A write access to the error
counters is only possible in test error mode (The [CANxMCR]<TSTERR> bit is "1"). In the case of a write to the
[CANxCEC] register, the write data to the lower 8 bits <REC[7:0]> is written also to the higher 8 bits
<TEC[7:0]>.
The CAN error counters count up or down according to the CAN Specification 2.0B.
The [CANxCEC]<REC[7:0]> is not increased after exceeding the error passive limit (128). When
[CANxCEC]<REC[7:0]>=128, after the correct reception of a message, the [CANxCEC]<REC[7:0]> is set to a
value between 119 and 127. After reaching the "bus off" status, the error counters are undefined.
If the status "bus off" is reached, the reception error counter is incremented after 11 consecutive recessive bits on
the bus. If the counter reaches the count 128, the module changes automatically to the status error active.
All internal flags are reset and the error counters will be cleared to "0". The configuration registers keep the
programmed values. The values of the counters are undefined during "bus off" status.
When CAN enters configuration mode, the error counters will be cleared.
R Read as "0".
R 8-bit transmission error counter (After reset release)
W 8-bit transmission error counter ([CANxMCR]<TSTERR>=1)
R 8-bit reception error counter (After reset release)
W 8-bit reception error counter ([CANxMCR]<TSTERR>=1)
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Function
TXZ+ Family
CAN Controller
2020-10-01
Rev. 1.0