Toshiba TXZ+ Series Reference Manual
2-bit risc microcontroller
Hide thumbs
Also See for TXZ+ Series:
- Reference manual (52 pages) ,
- Reference manual (88 pages) ,
- Reference manual (72 pages)
Table of Contents
Advertisement
Quick Links
Advertisement
Table of Contents
Related Manuals for Toshiba TXZ+ Series
Summary of Contents for Toshiba TXZ+ Series
- Page 1 TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 32-bit RISC Microcontroller TXZ+ Family TMPM4K Group(2) Reference Manual Clock Control and Operation Mode (CG-M4K(2)-E) Revision 1.1 2021-06 2021-06-15 1 / 64 © 2020-2021 Toshiba Electronic Devices & Storage Corporation Rev. 1.1...
-
Page 2: Table Of Contents
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode Contents Preface ................................. 6 Related documents ..............................6 Conventions ................................7 Terms and Abbreviations ............................9 Clock control and operation mode ......................10 1.1. Outlines ................................10 1.2. Clock control ..............................11 1.2.1. - Page 3 TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 1.4.2. Detail of Register ................................ 31 1.4.2.1. [CGPROTECT] (CG write protection register) ....................... 31 1.4.2.2. [CGOSCCR] (Oscillation control register) ........................31 1.4.2.3. [CGSYSCR] (System clock control register) ........................32 1.4.2.4. [CGSTBYCR] (Standby control register) ........................33 1.4.2.5.
- Page 4 TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 3.2.5. About turn on power supply after turn off ........................61 3.2.6. After reset release ..............................61 3.2.6.1. The reset factor and the reset range ..........................62 Revision History ............................63 RESTRICTIONS ON PRODUCT USE .......................
- Page 5 TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode List of Figures Figure 1.1 Clock system diagram......................12 Figure 1.2 Mode State Transition ......................25 Figure 1.3 NORMAL >>> STOP1 >>> NORMAL Operation mode transition ......... 29 Figure 2.1 TMPM4KxFYA ........................44 Figure 2.2 TMPM4KxFWA ........................
-
Page 6: Preface
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode Preface Related documents Document name documentation set for the Arm Cortex ® ® Exception Oscillation Frequency Detector Voltage Detection Circuit Clock Selective Watchdog Timer Flash Memory The datasheet of each product (Electrical Characteristics) 2021-06-15 6 / 64 Rev. -
Page 7: Conventions
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode Conventions ● Numeric formats follow the rules as shown below: Hexadecimal: 0xABC Decimal: 123 or 0d123 – Only when it needs to be explicitly shown that they are decimal numbers. Binary: 0b111 – It is possible to omit the "0b" when the number of bit can be distinctly understood from a sentence. - Page 8 TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode *********************************************************************************************************************** Arm, Cortex and Thumb are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All rights reserved. *********************************************************************************************************************** All other company names, product names, and service names mentioned herein may be trademarks of their respective companies.
-
Page 9: Terms And Abbreviations
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode Terms and Abbreviations Some of abbreviations used in this document are as follows: Analog to Digital Converter A-ENC32 Advanced Encoder input Circuit (32-bit) A-PMD Advanced Programmable Motor Control Circuit A-VE+ Advanced Vector Engine Plus Clock Control and Operation Mode Cyclic Redundancy Check D-Bus... -
Page 10: Clock Control And Operation Mode
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 1. Clock control and operation mode 1.1. Outlines The clock/mode control block can select a clock gear and prescaler clock, and set the warming-up of oscillator and so on. Furthermore, it has Normal mode and a low power consumption mode in order to reduce power consumption using mode transition. -
Page 11: Clock Control
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 1.2. Clock control 1.2.1. Clock type This section shows a list of clocks: EHCLKIN : The high speed clock input from the external fosc : A clock generated in the internal oscillation circuit or input from the X1 and X2 pins after being selected by [CGOSCCR]<OSCSEL>. -
Page 12: Clock System Diagram
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 1.2.3. Clock System diagram The figure below shows a clock system diagram. [CGWUPHCR]<WUON> [CGWUPHCR]<WUPT[15:4]> [CGSPCLKEN] <ADCKEN[3:0]> High speed ADCLK Warming-up timer [CGWUPHCR] <WUCLK> Peripheral function using fc DNF, OFD(Target clock) [CGOSCCR]<IHOSC1EN> [CGFCEN] <FCIPEN[31:0]>... -
Page 13: Warming-Up Function
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 1.2.4. Warming-up function A warming-up function starts the warming-up timer for high speed oscillator automatically to secure the oscillation stable time when the STOP1 mode is released. It is also available as a count-up timer which uses the warming-up timer for high speed oscillator to secure the stability of an external oscillator or an internal oscillator. -
Page 14: The Directions For A Warming-Up Timer
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 1.2.4.2. The directions for a warming-up timer The directions for a warming-up function are explained. Selection of a clock In a high speed oscillation, the clock classification (internal oscillation/external oscillation) counted with a warming-up timer is selected by [CGWUPHCR]<WUCLK>. -
Page 15: The Formula And The Example Of A Setting Of A Pll Multiplication Value
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 1.2.5.2. The formula and the example of a setting of a PLL multiplication value The details of the items of [CGPLL0SEL]<PLL0SET[23:0]> which set up a PLL multiplication value are shown below. Table 1.1 Details of [CGPLL0SEL]<PLL0SET[23:0]>... -
Page 16: Change Of The Pll Multiplication Value Under Operation
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode The main examples of a setting of [CGPLL0SEL]<PLL0SET[23:0]> are shown below. It multiplies by PLL, and dividing is carried out and the target Clock frequency (f ) is generated for input frequency (fosc). -
Page 17: Pll Operation Start / Stop / Switching Procedure
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 1.2.5.4. PLL operation start / stop / switching procedure (1) fc setup (PLL stop >>> PLL start) As an fc setup, the example of switching procedure from the PLL stop state to the PLL operation state is as follows. -
Page 18: System Clock
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 1.2.6. System clock An internal high speed oscillation clock or external high speed oscillation clock (connected oscillator or clock input) can be used as a source of system clock. The system clock consists of "High speed system clock (fsysh)(maximum 160MHz)" for high speed operation and "Middle speed system clock (fsysm)(maximum 80MHz)"... -
Page 19: The Setting Method Of A System Clock
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode Table 1.7 Operating frequency examples of High speed and Middle speed system clocks Middle speed system clock High speed fsysm (MHz) system clock fsysh (MHz) Note: The maximum frequency of Middle speed system clock is 80 MHz. 1.2.6.1. -
Page 20: Fosc Setup (Internal Oscillation >>> External Clock Input)
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode (2) fosc setup (Internal oscillation >>> External clock input) As a fosc setup, the example of switching procedure to the external clock input (EHCLKIN) from an internal oscillator1(IHOSC1) is shown below. <<... -
Page 21: Clock Supply Setting Function
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 1.2.7. Clock supply setting function This MCU has the clock supply on/off function for the peripheral circuits. To reduce the power consumption, this MCU can stop supplying the clock to the peripheral functions that are not used. Except some peripheral functions, clocks are not supplied after reset. -
Page 22: Operation Mode
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 1.3. Operation mode There are NORMAL mode and a Low Power consumption mode (IDLE, STOP1) in this product as an Operation mode, and it can reduce power consumption by performing mode changes according to directions for use. 1.3.1. -
Page 23: Transition To And Return From Low Power Consumption Mode
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 1.3.1.2. Transition to and Return from Low Power Consumption mode In order to shift to each Low Power Consumption mode, the IDLE/STOP1 mode is chosen by standby control register [CGSTBYCR]<STBY[1:0]>, and a WFI (Wait For Interrupt) command is executed. When the transition to the low power consumption mode has been done by WFI instruction, the return from the mode can be done by the reset or an interrupt generation. -
Page 24: The Peripheral Function State In A Low Power Consumption Mode
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 1.3.1.4. The peripheral function state in a Low Power Consumption mode The following Table 1.10 shows the Operation State of the peripheral function (block) in each mode. In addition, after reset release, it will be in the state where a clock is not supplied except for some blocks. If needed, set up [CGFSYSENA], [CGFSYSMENA], [CGFSYSMENB], [CGFCEN], [CGSPCLKEN] and enable clock supply. -
Page 25: Mode State Transition
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 1.3.2. Mode State Transition Reset After reset, the high speed oscillator1 (IHOSC1) oscillates. (Note2) Interrupt NORMAL STOP1 Mode Mode (CPU stops except some peripheral functions) Instruction (Note1) Instruction Interrupt IDLE Mode (CPU stops) (Operating peripheral function can be selected) -
Page 26: Stop1 Mode Transition Flow
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 1.3.2.2. STOP1 mode transition flow Set up the following procedure at switching to STOP1. Because STOP1 mode is released by an interrupt, set the interrupt before switching to STOP1 mode. For the interrupts that can be used to release the STOP1 mode, refer to "1.3.3.1. -
Page 27: Return From A Low Power Consumption Mode
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 1.3.3. Return from a Low Power Consumption mode 1.3.3.1. The release source of a Low Power Consumption mode Interrupt, Non-Maskable Interrupt, and reset can perform return from a Low Power Consumption mode. The standby release source which can be used is decided by a Low Power Consumption mode. -
Page 28: Warming-Up At The Release Of Low Power Consumption Mode
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode ● Released by an interrupt request When interrupt cancels a Low Power Consumption mode, it is necessary to prepare so that interrupt may be detected by CPU. The interrupt used for release in STOP1 mode needs to set up CPU, and needs to set up detection by INTIF. -
Page 29: Clock Operation By Mode Transition
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 1.3.4. Clock operation by mode transition The clock operation in case of mode transition is shown below. 1.3.4.1. NORMAL >>> IDLE >>> NORMAL Operation mode transition CPU stops at IDLE mode. The clock supply to a peripheral function holds a setting state. Please perform operation/stop by the register of each peripheral function, a clock supply setting function, etc. -
Page 30: Explanation Of Register
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 1.4. Explanation of Register 1.4.1. Register list The register related to CG and its address information are shown below. Peripheral function Channel/Unit Base address Clock Control and Operation Mode 0x40083000 Register name Address (Base+) CG write protection register [CGPROTECT]... -
Page 31: Detail Of Register
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 1.4.2. Detail of Register 1.4.2.1. [CGPROTECT] (CG write protection register) Bit Symbol After reset Type Function 31:8 Read as "0" Control write-protection for the CG register (all registers included except this register) PROTECT[7:0] 0xC1 0xC1: CG Registers are write-enabled. -
Page 32: Cgsyscr] (System Clock Control Register)
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode Note3: When using the oscillator connection, set this bit to "01" (external high speed oscillator). Note4: To wait stabilizing oscillation of an internal high speed oscillator1 (IHOSC1), use a warming-up timer and confirm [CGWUPHCR]<WUEF>... -
Page 33: Cgstbycr] (Standby Control Register)
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 1.4.2.4. [CGSTBYCR] (Standby control register) Bit Symbol After reset Type Function 31:2 Read as "0" Selects a low power consumption mode. 00: IDLE STBY[1:0] 01: STOP1 10: Reserved 11: Reserved 1.4.2.5. [CGPLL0SEL] (PLL selection register for fsys) Bit Symbol After reset Type... -
Page 34: Cgwuphcr] (High Speed Oscillation Warming-Up Register)
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 1.4.2.6. [CGWUPHCR] (High speed oscillation warming-up register) Bit Symbol After reset Type Function Sets the upper 12 bits of the 16 bits of calculation values of the warming-up timer. 31:20 WUPT[15:4] 0x800 About a setup of a warming-up timer, refer to "1.2.4.1. - Page 35 TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode Bit Symbol After reset Type Function Clock enable of UART ch3 (TSEL24) IPMENA24 0: Clock stop 1: Clock supply Clock enable of UART ch2 (TSEL23) IPMENA23 0: Clock stop 1: Clock supply Clock enable of UART ch1 (TSEL22) IPMENA22 0: Clock stop...
- Page 36 TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode Bit Symbol After reset Type Function Clock enable of PORT F IPMENA05 0: Clock stop 1: Clock supply Clock enable of PORT E IPMENA04 0: Clock stop 1: Clock supply Clock enable of PORT D IPMENA03 0: Clock stop 1: Clock supply...
-
Page 37: Cgfsysmenb] (Supply And Stop Register B For Fsysm)
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 1.4.2.8. [CGFSYSMENB] (Supply and stop register B for fsysm) Bit Symbol After reset Type Function Clock enable of SIWDT ch0 IPMENB31 0: Clock stop 1: Clock supply Clock enable of NBDIF IPMENB30 0: Clock stop 1: Clock supply... -
Page 38: Cgfsysena] (Supply And Stop Register A For Fsysh)
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode Bit Symbol After reset Type Function Clock enable of A-ENC32 ch1 IPMENB07 0: Clock stop 1: Clock supply Clock enable of A-ENC32 ch0 IPMENB06 0: Clock stop 1: Clock supply Clock enable of OPAMP Unit A/B/C IPMENB05 0: Clock stop 1: Clock supply... -
Page 39: Cgfcen] (Clock Supply And Stop Register For Fc)
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 1.4.2.10. [CGFCEN] (Clock supply and stop register for fc) Bit Symbol After reset Type Function 31:29 Read as "0" Clock enable of DNF Unit C (INT21) FCIPEN28 0: Clock stop 1: Clock supply Clock enable of DNF Unit B (INT08b to 18) FCIPEN27 0: Clock stop... -
Page 40: Information According To Product
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 1.5. Information according to product The information about [CGFSYSMENA], [CGFSYSMENB], [CGFSYSENA] and [CGFCEN] which are different according to each product is shown below. 1.5.1. [CGFSYSMENA] Table 1.13 [CGFSYSMENA] register corresponding to each product Channel No./ Internal connection Bit Symbol... -
Page 41: Cgfsysmenb]
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 1.5.2. [CGFSYSMENB] Table 1.14 [CGFSYSMENB] register corresponding to each product Channel No./ Internal connection Bit Symbol Unit name / M4KN M4KM M4KL M4KH peripheral circuit Port name IPMENB31 SIWDT ... -
Page 42: Cgfsysena]
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 1.5.3. [CGFSYSENA] Table 1.15 [CGFSYSENA] register corresponding to each product Channel No./ Internal connection Bit Symbol Unit name / M4KN M4KM M4KL M4KH peripheral circuit Port name IPENA01 RAMP ... -
Page 43: Memory Map
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 2. Memory map 2.1. Outlines The memory maps for TMPM4K Group(2) are based on the Arm Cortex-M4(with FPU) processor core memory map. The internal ROM, internal RAM and special function registers (SFR) of TMPM4K Group(2) are mapped to the Code, SRAM and peripheral regions of the Cortex-M4(with FPU) respectively. -
Page 44: Tmpm4Kxfya
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 2.1.1. TMPM4KxFYA - Code Flash 256KB - RAM 24KB - Data Flash 32KB TMPM4KHFYAUG, TMPM4KLFYAFG, TMPM4KLFYAUG, TMPM4KMFYAFG, - Products TMPM4KNFYAFG, TMPM4KNFYADFG 0xFFFFFFFF 0xFFFFFFFF Vender-Specific Vender-Specific 0xE0100000 0xE0100000 CPU Register CPU Register Region Region 0xE0000000... -
Page 45: Tmpm4Kxfwa
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 2.1.2. TMPM4KxFWA - Code Flash 128KB - RAM 24KB - Data Flash 32KB TMPM4KHFWAUG, TMPM4KLFWAFG, TMPM4KLFWAUG, TMPM4KMFWAFG, - Products TMPM4KNFWAFG, TMPM4KNFWADFG 0xFFFFFFFF 0xFFFFFFFF Vender-Specific Vender-Specific 0xE0100000 0xE0100000 CPU Register CPU Register Region Region 0xE0000000... -
Page 46: Bus Matrix
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 2.2. Bus Matrix TMPM4K Group(2) contains the CPU Core of the main master and sub masters. The sub masters include DMA controller (DMAC) and NBDIF. Main masters connect to slave ports (S0 to S3) of Bus Matrix. In the bus matrix, master ports (M0 to M9) connect to peripheral functions via connections described as (○) or (●) in the following figure. -
Page 47: Structure
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 2.2.1. Structure 2.2.1.1. Single Chip Mode Cortex-M4(with FPU) S-Bus D-Bus I-Bus Code Flash Data Flash (Note) Boot ROM RAM0 RAMP(ch0) RAM1 IB(INTIF) IMN(INTIF) Clock Clock Synchronous Synchronous circut circut DMAC NBDIF IA(INTIF) RAM2 TSPI... -
Page 48: Single Boot Mode
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 2.2.1.2. Single Boot Mode Cortex-M4(with FPU) S-Bus D-Bus I-Bus Code Flash Data Flash (Note) Boot ROM RAM0 RAMP(ch0) RAM1 IB(INTIF) IMN(INTIF) Clock Clock Synchronous Synchronous circuit circuit DMAC NBDIF IA(INTIF) RAM2 TSPI OPAMP T32A... -
Page 49: Connection Table
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 2.2.2. Connection table 2.2.2.1. Connection of Memory related (1) TMPM4KxFYA ● Single Chip Mode Table 2.1 Single Chip Mode Sub master Main master Core Core Core Start Address Slave DMAC NBDIF S-Bus D-Bus I-Bus... -
Page 50: Table 2.3 Single Chip Mode
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode (2) TMPM4KxFWA ● Single Chip Mode Table 2.3 Single Chip Mode Sub master Main master Core Core Core Start Address Slave DMAC NBDIF S-Bus D-Bus I-Bus Fault Fault Fault 0x00000000 Code Flash Fault Fault... -
Page 51: Connection Of Peripheral Function
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 2.2.2.2. Connection of peripheral function Table 2.5 Connection of peripheral function Sub master Main master Core Core Core Start Address Slave DMAC NBDIF S-Bus D-Bus I-Bus 0x40000000 Fault Fault Fault Fault 0x40005000 Reserved 0x40006000... -
Page 52: Reset And Power Supply Control
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 3. Reset and power supply control 3.1. Outlines Function classification Factor Functional Description Reset which occurs at the time of a power supply turning Power On Reset on or turning off. LVD reset Reset which occurs below the set-up voltage Cold reset... -
Page 53: Reset By A Power On Reset Circuit (Without Using A Reset_N Pin)
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 3.2.1.1. Reset by a Power On Reset Circuit (without using a RESET_N pin) After a supply voltage exceeds the release voltage of a Power On Reset (POR), internal reset is deasserted after "Internal initialization time"... -
Page 54: Reset By A Reset_N Pin
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 3.2.1.2. Reset by a RESET_N pin When turn on a power supply, it can control the timing of reset release by using RESET_N pin. After a supply voltage exceeds the release voltage of a Power On Reset and even after "Internal initialization time" elapsed, if the RESET_N pin is "Low", internal reset continues. -
Page 55: Figure 3.3 Reset Operation By A Reset_N Pin (2)
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode In case of RESET_N pin input change from "Low" to "High" before "Internal initialization time" elapses, internal reset signal is released after "Internal initialization time" elapses. Please goes up a supply voltage into an operating voltage range before "Internal initialization time" elapses. The CPU operates after internal reset release. -
Page 56: Continuation Of Reset By Lvd
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 3.2.1.3. Continuation of reset by LVD When the power supply voltage has not exceeded the LVD release voltage even after "Internal initialization time" elapsed, LVD generates the reset signal and the reset state continues. After the power supply voltage exceeds the LVD release voltage and "LVD detection release time"... -
Page 57: Warm Reset
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 3.2.2. Warm reset 3.2.2.1. Warm reset by RESET_N pin When resetting with the RESET_N pin, set the RESET_N pin to "Low" for 17.2 µs or more while the power supply voltage is within the operating range. When the "Low"... -
Page 58: Starting In Single Boot Mode
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 3.2.3. Starting in Single Boot Mode Refer to the reference manual "Flash Memory" for details of "Single Boot Mode". 3.2.3.1. Starting by the RESET_N pin When "Low" is inputted to a BOOT_N pin, if reset is released (a RESET_N pin "Low" to "High"), "Single Boot Mode"... -
Page 59: Starting In Single Boot Mode When Power Supply Is Stable
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 3.2.3.2. Starting in Single Boot Mode when power supply is stable When the supply voltage is stable within an operating voltage range, input "Low" to RESET_N pin for reset longer than "Internal processing time", while "Low" is inputted to the BOOT_N pin. And release reset (RESET_N pin to "High"). -
Page 60: Power On Reset Circuit
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 3.2.4. Power On Reset Circuit The Power On Reset Circuit (POR) generates a reset signal when the power is turned on or turned off. Note: The Power On Reset Circuit may not operate correctly due to the fluctuation of the power supply. Equipment should be designed with full consideration of the electrical characteristics. -
Page 61: About Turn On Power Supply After Turn Off
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 3.2.5. About turn on power supply after turn off When using external reset circuit or internal LVD reset output When the power supply is turned off and the power supply voltage drops below the operation guaranteed voltage, reset is performed with an external reset circuit or built-in LVD (when the voltage is less than the set voltage). -
Page 62: The Reset Factor And The Reset Range
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 3.2.6.1. The reset factor and the reset range Reset factors and the range initialized are shown in Table 3.1. Table 3.1 The reset factor and the range initialized Reset factors Cold Warm Reset Reset Registers and... -
Page 63: Revision History
TXZ+ Family TMPM4K Group(2) Clock Control and Operation Mode 4. Revision History Table 4.1 Revision History Revision Date Description 2021-02-09 - First release - 1.3.4.2 NORMAL >>> STOP1 >>> NORMAL Operation mode transition Added note. - 3.2.2.2. Warm reset by LVD Added chapter 2021-06-15 - 3.2.2.3. -
Page 64: Restrictions On Product Use
Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application with which the Product will be used with or for.