[Canxtsp](Time Stamp Counter Prescaler Register); [Canxtsc](Time Stamp Counter Register) - Toshiba TXZ+ Series Reference Manual

[CANxTSP](Time Stamp Counter Prescaler Register)

Bit Bit Symbol After Reset Type
31:4 - 0
3:0 TSP[3:0] 0
To ensure that the value of the [CANxTSC] will not change during the write cycle to the mailbox, a hold register
is implemented. The value of the [CANxTSC] will be copied to the hold register and then written to the mailbox
from the hold register if a message has been received or transmitted successfully. The reception is successful for
the receiver, if there is no error but the last one bit of End-of-frame. Transmission is successful for the transmitter
if there is no error until the last bit of End-of-frame. (Refer to the CAN specification 2.0B).

[CANxTSC](Time Stamp Counter Register)

Bit Bit Symbol After Reset Type
31:16 - 0
15:0 TSC[15:0] 0
The overflow of the [CANxTSC] can be detected by the time stamp counter overflow interrupt flag <TSOIF> of
the global interrupt flag register [CANxGIF], and the time stamp counter overflow flag <TSO> of the global
status register [CANxGSR]. Both flags can be cleared by writing "1" to <TSOIF> in the [CANxGIF] register.
There is a 4-bit prescaler for the [CANxTSC]. After power-up the time stamp counter is driven directly from the
bit clock ([CANxTSP]<TSP[3:0]>=0). The period T
following formula:
T = TBIT × ([CANxTSP]<TSP[3:0]> + 1)
TSC
R Read as "0".
Time stamp counter prescaler
R/W
Sets the value to be loaded to the prescaler for the 4-bit TSC.
R Read as "0".
Time stamp counter
R
Free running 16-bit counter
TSC
47 / 52
Function
Function
for the time stamp counter will be calculated by the
TXZ+ Family
CAN Controller
2020-10-01
Rev. 1.0