Toshiba TXZ+ Series Reference Manual
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- Page 1 TXZ+ Family CAN Controller 32-bit RISC Microcontroller TXZ+ Family Reference Manual CAN Controller (CAN-B) Revision 1.0 2020-10 2020-10-01 1 / 52 © 2020 Rev. 1.0 Toshiba Electronic Devices & Storage Corporation...
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Page 2: Table Of Contents
TXZ+ Family CAN Controller Contents Preface ................................. 5 Related document ..............................5 Conventions ................................6 Terms and Abbreviations ............................8 Outlines ................................. 9 Block Diagram ............................. 10 Function and Operation ..........................11 3.1. Clock Supply ..............................11 3.2. CAN Interface ..............................11 3.3. - Page 3 TXZ+ Family CAN Controller [CANxGAM](Global Acceptance Mask Register) ...................... 38 [CANxMCR](Master Control Register) ........................39 [CANxGSR](Global Status Register) ........................40 [CANxBCR1](Bit Configuration Register1) ....................... 41 [CANxBCR2](Bit Configuration Register2) ....................... 41 [CANxGIF](Global Interrupt Flag Register) ....................... 42 [CANxGIM](Global Interrupt Mask Register)......................43 [CANxMBTIF](Mailbox Transmit Interrupt Flag Register) ..................
- Page 4 TXZ+ Family CAN Controller List of Figures Figure 2.1 Block Diagram of CAN controller .................... 10 Figure 3.1 Configuration of Mailboxes ..................... 12 Figure 3.2 Timing when a Receive Message Lost Occurs ..............14 Figure 3.3 Receive filtering ........................16 Figure 3.4 Timer Stamp Counter......................
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Page 5: Preface
TXZ+ Family CAN Controller Preface Related document Document Name Clock Control and Operation Mode Input/Output ports Product Information 5 / 52 2020-10-01 Rev. 1.0... -
Page 6: Conventions
TXZ+ Family CAN Controller Conventions Numeric formats follow the rules as shown below: Hexadecimal: 0xABC Decimal: 123 or 0d123 – Only when it needs to be explicitly shown that they are decimal numbers. Binary: 0b111 – It is possible to omit the "0b" when the number of bit can be distinctly understood from a sentence. - Page 7 TXZ+ Family CAN Controller All other company names, product names, and service names mentioned herein may be trademarks of their respective companies. 7 / 52 2020-10-01 Rev. 1.0...
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Page 8: Terms And Abbreviations
TXZ+ Family CAN Controller Terms and Abbreviations Some of abbreviations used in this document are as follows: Controller Area Network 8 / 52 2020-10-01 Rev. 1.0... -
Page 9: Outlines
TXZ+ Family CAN Controller 1. Outlines The CAN can operate as a transmission/ reception circuit of 1channel per unit. The following shows the List of Function. Function Function Operation explanation classification Compliant with CAN version 2.0B active Standard and extended formats supported Max 1Mbps (fsys=48MHz(Min)) Protocol CAN bus bit rate... -
Page 10: Block Diagram
TXZ+ Family CAN Controller 2. Block Diagram Figure 2.1 shows the Block Diagram of CAN controller CANxCLK Control & Interrupt INTCANxRXD INTCANxTXD INTCANxGLB Transmit buffer Transmit data Control CANxTX interface CAN protocol controller CANxRX Receive data Prio rity comparison regi ster Receive buffer Mailbox Data output... -
Page 11: Function And Operation
TXZ+ Family CAN Controller 3. Function and Operation 3.1. Clock Supply When you use CAN, please set an applicable clock enable bit to "1" (clock supply) in fsys supply stop register A ([CGFSYSENA], [CGFSYSMENA]), fsys supply stop register B ([CGFSYSENB], [CGFSYSMENB]), fsys supply stop register C([CGFSYSMENC]), and fc supply stop registers ([CGFCEN]). -
Page 12: Function
TXZ+ Family CAN Controller 3.3. Function Mailbox The mailboxes consist of a single port RAM (accessible from the internal CAN core and the CPU). The CPU controls the CAN controller by changing the settings of the mailboxes and control registers. The settings of the mailboxes and control registers are used for such processes as reception filtering, message transmission, and interrupt processing. -
Page 13: Transmit Control Register
TXZ+ Family CAN Controller Transmit Control Register Transmission control consists of two registers. One is the transmission request set register [CANxTRS], and the other is the transmission request reset register [CANxTRR]. Therefore it is possible to clear the transmission request without generating a conflict in the handling of the transmission mailboxes in the state-machine. This mechanism also prevents clearing the transmission request of a mailbox to which transmission is already in progress. -
Page 14: Receive Control Register
TXZ+ Family CAN Controller Receive Control Register The ID of a received message is compared to the ID of the mailbox set as the receive mailbox. The comparison of the IDs depends on the [CANxMBnID]<GAME_LAME> values of the global/local acceptance mask enable bit and the data held in the global/local acceptance mask registers [CANxGAM]/[CANxLAM]. -
Page 15: Remote Frame Control Register
TXZ+ Family CAN Controller Remote Frame Control Register After a remote frame is received, the remote frame ID is compared to the mailbox ID. The comparison of the IDs depends on the value of the global/local acceptance mask enable bit [CANxMBnID]<GAME_LAME> in the mailbox and the data held in the global/local acceptance mask registers [CANxGAM]/[CANxLAM]. -
Page 16: Receive Filtering
TXZ+ Family CAN Controller Receive Filtering For mailboxes 0 to 30, the global acceptance mask register [CANxGAM] will be used if the global bit in the mailbox is set. The receiving message will be stored in the first mailbox with a matching ID. Only if there is no matching ID in the mailboxes 0 to 30, the receiving message will be compared to the receive-only mailbox (mailbox 31). -
Page 17: Time Stamp Function
TXZ+ Family CAN Controller Time Stamp Function There is a free-running 16-bit time stamp counter [CANxTSC] implemented in the CAN controller to show the time of message reception and transmission. The content of the [CANxTSC] is written into the time stamp value (TSV) of the corresponding mailbox when a received message has been stored or a message has been transmitted. -
Page 18: Interrupt Control
TXZ+ Family CAN Controller Interrupt Control The CAN controller has the following interrupt factors. And these interrupt factors are divided into three groups and each group has one interrupt output. ● CANx transmission completion interrupt (INTCANxTXD) It occurs at the completion of transmission. ●... -
Page 19: Figure 3.5 Block Diagram Of Canx Interrupt Signals
TXZ+ Family CAN Controller <MBRIF[31]> <MBIM[31]> <MBRIF[30]> INTCANxRXD <MBIM[30]> Pulse <MBTIF[30]> INTCANxTXD INTCANxGLB 32 sources for receive 31 sources for transmit Pulse <MBRIF[0]> <MBIM[0]> <MBTIF[0]> [CANxGIF]<RFPF> [CANxGIM]<RFPM> Pulse 8 sources from global interrupt [CANxGIF]<WLIF> [CANxGIM]<WLIM> Figure 3.5 Block Diagram of CANx interrupt signals The CANx reception completion interrupt signal INTCANxRXD is the OR of the signal for which the 32 factors issued by the mailbox receive interrupt flag register [CANxMBRIF] that are ANDed with each bit of the mailbox interrupt mask register [CANxMBIM]. -
Page 20: Operation Mode
TXZ+ Family CAN Controller 3.4. Operation Mode Configuration Mode The CAN controller needs initial setup before starting operation (setting of the bit configuration registers, [CANxBCR1] and [CANxBCR2]). Writes to the [CANxBCR1] and [CANxBCR2] are possible only when the CAN controller is in configuration mode. After reset, the [CANxMCR]<CCR>... -
Page 21: Figure 3.6 Flowchart Of Initial Setup Of Can Controller
TXZ+ Family CAN Controller Switch to configuration mode Initialize CAN after reset from normal operation mode CAN is in configuration mode: CAN is in normal operation mode: [CANxMCR]<CCR> = 1 & [CANxMCR]<CCR> = 0 & [CANxGSR]<CCE> = 1 [CANxGSR]<CCE> = 0 Set bit timing parameters in Configuration mode [CANxBCR1] &... -
Page 22: Sleep Mode
TXZ+ Family CAN Controller Sleep Mode Sleep mode is requested by a write of "1" to the [CANxMCR]<SMR> bit. After the CAN controller has entered into sleep mode, the [CANxGSR]<SMA> bit is set to "1". The read value of the [CANxGSR] register is "0x0001F040". This means that there is no message in the transmission buffer and sleep mode is active where the <SMA>... -
Page 23: Test Loop Back Mode
TXZ+ Family CAN Controller Test Loop Back Mode In test loop back mode, the CAN controller can receive its own transmitted message and generates its own acknowledge bit. No other CAN node is necessary for the operation. The test loop back mode can be enabled or disabled only when the CAN controller is in suspend mode. In test loop back mode, the CAN controller can transmit a message from a mailbox and receive it in another mailbox. -
Page 24: Bit Configuration
TXZ+ Family CAN Controller 3.5. Bit Configuration The bit length is determined by the parameters [CANxBCR2]<TSEG1>, [CANxBCR2]<TSEG2>, and [CANxBCR1]<BRP>. All controllers on the CAN bus must have the same baud rate and bit length. At different clock frequencies of the individual controllers, the baud rate has to be adjusted by the above-mentioned parameters. -
Page 25: Table 3.2 Restrictions When Setting The Baud Rate
TXZ+ Family CAN Controller Information processing time (IPT) is the time segment starting with the sample point reserved for processing of the sampled bit level. The information processing time is equal to three CAN system clock cycles. [CANxBCR2]<SJW[1:0]> indicates how much the time quantum (T ) value in bit length is allowed to be lengthened or shortened when resynchronizing. -
Page 26: Register
TXZ+ Family CAN Controller 4. Register 4.1. Register list The control registers and their addresses are shown as follows: Base address Function Channel/Unit TYPE 1 unit A 0x40005000 CAN controller unit B 0x40006000 Register Name Address(+Base) CAN Mailbox Refer to "4.1.1" 0x0000 to 0x03E0 Mailbox Configuration Register [CANxMC]... -
Page 27: Can Mailbox
TXZ+ Family CAN Controller CAN Mailbox The address of each mailbox is as follows. Function name Mailbox No. Address(+Base) No.0 0x0000 No.1 0x0020 No.2 0x0040 No.3 0x0060 No.4 0x0080 No.5 0x00A0 No.6 0x00C0 No.7 0x00E0 No.8 0x0100 No.9 0x0120 No.10 0x0140 No.11 0x0160... -
Page 28: Details Of Registers
TXZ+ Family CAN Controller 4.2. Details of Registers [CANxMBnID](Message ID Field Register) Bit Symbol After Reset Type Function ID Extension bit 0: Standard format (11-bit ID) from <ID28> to <ID18> used 1: Extended format (29-bit ID) from <ID28> to <ID0> used Sets the mailbox by selecting whether to receive or transmit the extended format (<IDE>=1) or the standard format (<IDE>=0). -
Page 29: [Canxmbntsvmcf](Time Stamp Values Message Control Field Register)
TXZ+ Family CAN Controller [CANxMBnTSVMCF](Time Stamp Values Message Control Field Register) Bit Symbol After Reset Type Function Time stamp counter value When message have been successfully received or transmitted, the 16-bit time stamp counter 31:16 TSV[15:0] values are stored. No value is set when message reception or transmission fails. For the details of the entire time stamp counter function, Refer to "3.3.6Time Stamp Function". -
Page 30: [Canxmbndl](Data Fields Register )
TXZ+ Family CAN Controller [CANxMBnDL](Data fields Register ) Bit Symbol After Reset Type Function 31:24 D3[7:0] Transmitted or received data is stored. 23:16 D2[7:0] Transmitted or received data is stored. 15:8 D1[7:0] Transmitted or received data is stored. D0[7:0] Transmitted or received data is stored. For transmission, data is transmitted according to the data byte count set in the [CANxMBnTSVMCF]<DLC[3:0]>... -
Page 31: [Canxmc](Mailbox Configuration Register)
TXZ+ Family CAN Controller [CANxMC](Mailbox Configuration Register) Bit Symbol After Reset Type Function Access configuration to the mailbox (Each bit corresponds to mailboxes 31 to 0) 0: The corresponding mailbox MBn is disabled for the CAN controller. 1: The corresponding mailbox MBn is enabled for the CAN controller. Write access from CPU 31:0 MC[31:0]... -
Page 32: [Canxtrs](Transmission Request Set Register)
TXZ+ Family CAN Controller [CANxTRS](Transmission Request Set Register) Bit Symbol After Reset Type Function Read as "0" Transmit request set (Each bit corresponds to mailboxes 30 to 0.) Set <TRSn> requests the message transmission of corresponding mailbox n. When the transmission is requested for multiple mailboxes, the message is transmitted in 30:0 TRS[30:0] accordance with the priority corresponding to the [CANxMCR]<MTOS>... -
Page 33: [Canxtrr](Transmission Request Reset Register)
TXZ+ Family CAN Controller [CANxTRR](Transmission Request Reset Register) Bit Symbol After Reset Type Function Read as "0" Transmit request reset (Each bit corresponds to mailboxes 30 to 0.) Setting <TRRn> cancels the message transmission of corresponding mailbox n. 30:0 TRR[30:0] A write of "1"... -
Page 34: [Canxta](Transmission Acknowledge Register)
TXZ+ Family CAN Controller [CANxTA](Transmission Acknowledge Register) Bit Symbol After Reset Type Function Read as "0". Transmission acknowledge (Each bit corresponds to mailboxes 30 to 0) When the message in mailbox n has been successfully transmitted, the <TAn> bit is set to "1". 30:0 TA[30:0] The <TAn>... -
Page 35: [Canxrmp](Receive Message Pending Register)
TXZ+ Family CAN Controller [CANxRMP](Receive Message Pending Register) Bit Symbol After Reset Type Function Receive message pending (Each bit corresponds to mailboxes 31 to 0.) After a message is received and the content of the received message is written in mailbox n, the 31:0 RMP[31:0] <RMPn>... -
Page 36: [Canxrml](Receive Message Lost Register)
TXZ+ Family CAN Controller [CANxRML](Receive Message Lost Register) Bit Symbol After Reset Type Function Receive message lost (Each bit corresponds to mailboxes 31 to 0.) When mailbox n for which the <RMPn> bit is set to "1" receives the next message, the content of 31:0 RML[31:0] the received message is overwritten to the mailbox n, and the <RMLn>... -
Page 37: [Canxlam](Local Acceptance Mask Register)
TXZ+ Family CAN Controller [CANxLAM](Local Acceptance Mask Register) Bit Symbol After Reset Type Function Mask of the ID extension bit<IDE> (mailbox 31) 0: Not masked 1: Masked In case of <LAMI>=0, the message in the standard or the extended format is received, according LAMI to the <IDE>... -
Page 38: [Canxgam](Global Acceptance Mask Register)
TXZ+ Family CAN Controller [CANxGAM](Global Acceptance Mask Register) Bit Symbol After Reset Type Function Mask of the ID extension bit<IDE> (mailboxes 0 to 30) 0: Not masked 1: masked GAMI In case if <GAMI> =0, the message of the standard or the extended format is received, according to the <IDE>... -
Page 39: [Canxmcr](Master Control Register)
TXZ+ Family CAN Controller [CANxMCR](Master Control Register) Bit Symbol After Reset Type Function 31:12 Read as "0". Suspend mode request 0: Cancels suspend mode (normal operation) 1: Requests suspend mode Read as "0". Test loop back TSTLB 0: Cancels test loop back mode (normal operation) 1: Requests test loop back mode (This mode supports stand-alone operation.) Test error 0: Cancels test error mode (normal operation) -
Page 40: [Canxgsr](Global Status Register)
TXZ+ Family CAN Controller [CANxGSR](Global Status Register) Bit Symbol After Reset Type Function 31:17 Read as "0". Message in slot Indicates the mailbox number of a message located in the transmission buffer. 00000: Message for mailbox 0 01011: Message for mailbox 11 10110: Message for mailbox 22 00001: Message for mailbox 1 01100: Message for mailbox 12 10111: Message for mailbox 23 00010: Message for mailbox 2 01101: Message for mailbox 13 11000: Message for mailbox 24 00011: Message for mailbox 3 01110: Message for mailbox 14 11001: Message for mailbox 25... -
Page 41: [Canxbcr1](Bit Configuration Register1)
TXZ+ Family CAN Controller [CANxBCR1](Bit Configuration Register1) Bit Symbol After Reset Type Function 31:10 Read as "0". Set the value of Baud rate prescaler BRP[9:0] value: 0 to 1023 [CANxBCR2](Bit Configuration Register2) Bit Symbol After Reset Type Function 31:10 Read as "0". Resynchronization jump width 00: 1 ×... -
Page 42: [Canxgif](Global Interrupt Flag Register)
TXZ+ Family CAN Controller [CANxGIF](Global Interrupt Flag Register) Bit Symbol After Reset Type Function 31:8 Read as "0". Remote frame pending flag 0: No remote frame has been received. RFPF 1: Remote frames have been received. (in the receive mailbox) This bit will not be set when matching with the transmission mailbox for which the <RFH>... -
Page 43: [Canxgim](Global Interrupt Mask Register)
TXZ+ Family CAN Controller [CANxGIM](Global Interrupt Mask Register) Bit Symbol After Reset Type Function 31:8 Read as "0". Remote frame pending interrupt mask RFPM 0: Interrupt disable 1: Interrupt enable Wake-up interrupt mask WUIM 0: Interrupt disable 1: Interrupt enable Receive message lost interrupt mask RMLIM 0: Interrupt disable... -
Page 44: [Canxmbtif](Mailbox Transmit Interrupt Flag Register)
TXZ+ Family CAN Controller [CANxMBTIF](Mailbox Transmit Interrupt Flag Register) Bit Symbol After Reset Type Function Read as "0". Mailbox transmission interrupt flag (Each bit corresponds to mailboxes 30 to 0.) When the message in mailbox n has been successfully transmitted and the interrupt mask of the [CANxMBIM] register is enabled (<MBIMn>=1), the <MBTIFn>... -
Page 45: [Canxcdr](Change Data Request Register)
TXZ+ Family CAN Controller [CANxCDR](Change Data Request Register) Bit Symbol After Reset Type Function Read as "0". Change data request (Each bit corresponds to mailboxes 30 to 0.) When the <CDRn> bit of transmission mailbox n is set to "1", the transmission request of this mailbox n is ignored. -
Page 46: [Canxcec](Canx Error Counter Register)
TXZ+ Family CAN Controller [CANxCEC](CANx Error Counter Register) Bit Symbol After Reset Type Function 31:16 Read as "0". 8-bit transmission error counter (After reset release) 15:8 TEC[7:0] 8-bit transmission error counter ([CANxMCR]<TSTERR>=1) 8-bit reception error counter (After reset release) REC[7:0] 8-bit reception error counter ([CANxMCR]<TSTERR>=1) The CAN controller contains two error counters: the reception error counter <REC[7:0]>... -
Page 47: [Canxtsp](Time Stamp Counter Prescaler Register)
TXZ+ Family CAN Controller [CANxTSP](Time Stamp Counter Prescaler Register) Bit Symbol After Reset Type Function 31:4 Read as "0". Time stamp counter prescaler TSP[3:0] Sets the value to be loaded to the prescaler for the 4-bit TSC. To ensure that the value of the [CANxTSC] will not change during the write cycle to the mailbox, a hold register is implemented. -
Page 48: Usage
TXZ+ Family CAN Controller 5. Usage 5.1. Receive Messages Figure 5.1 shows an example flowchart of message reception using the CANx reception completion interrupt (INTCANxRXD). Receiving messages Setup a mailbox for message reception Disable mailbox: New setup for set [CANxMC]<MCn> to "0" the mailbox? Wait for INTCANxRXD... -
Page 49: Transmitting Message
TXZ+ Family CAN Controller 5.2. Transmitting Message Figure 5.2 shows an example flowchart of message transmission using the CANx transmission completion interrupt (INTCANxTXD). Setup a mailbox for Transmitting messages message transmission Disable mailbox: New setup for set [CANxMC]<MCn> to "0" the mailbox? Update mailbox data? -
Page 50: Remote Frame Handling
TXZ+ Family CAN Controller 5.3. Remote Frame Handling Figure 5.3 shows an example flowchart of remote frame handling by using the automatic reply feature. This feature is available when the [CANxMBnID]<RFH> bit of the transmission mailbox is set to "1". To avoid data inconsistency when updating the mailbox data, the [CANxCDR] register controls transmission during data update of the mailbox. -
Page 51: Revision History
TXZ+ Family CAN Controller 6. Revision History Table 6.1 Revision History Revision Date Description 2020-10-01 New Release 51 / 52 2020-10-01 Rev. 1.0... -
Page 52: Restrictions On Product Use
Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application with which the Product will be used with or for.