Quectel SC600Y-EM Series Hardware Design page 74

CSI1_LN0_P 185
CSI1_LN1_N 188
CSI1_LN1_P 187
CSI1_LN2_N 190
CSI1_LN2_P 189
CSI1_LN3_N 192
CSI1_LN3_P 191
CSI2_CLK_N 78
CSI2_CLK_P 77
CSI2_LN0_N 80
CSI2_LN0_P 79
CSI2_LN1_N 82
CSI2_LN1_P 81
CSI2_LN2_N 84
CSI2_LN2_P 83
CSI2_LN3_N 86
CSI2_LN3_P 85
MCAM_MCLK 99
SCAM_MCLK 100
SC600Y&SC600T_Hardware_Design
MIPI lane 0 data signal of
AI
depth camera (positive)
MIPI lane 1 data signal of
AI
depth camera (negative)
MIPI lane 1 data signal of
AI
depth camera (positive)
MIPI lane 2 data signal of
AI
depth camera (negative)
MIPI lane 2 data signal of
AI
depth camera (positive)
MIPI lane 3 data signal of
AI
depth camera (negative)
MIPI lane 3 data signal of
AI
depth camera (positive)
MIPI clock signal of front
AI
camera (negative)
MIPI clock signal of front
AI
camera (positive)
MIPI lane 0 data signal of
AI
front camera (negative)
MIPI lane 0 data signal of
AI
front camera (positive)
MIPI lane 1 data signal of
AI
front camera (negative)
MIPI lane 1 data signal of
AI
front camera (positive)
MIPI lane 2 data signal of
AI
front camera (negative)
MIPI lane 2 data signal of
AI
front camera (positive)
MIPI lane 3 data signal of
AI
front camera (negative)
MIPI lane 3 data signal of
AI
front camera (positive)
Master clock signal of rear
DO
camera
Master clock signal of front
DO
camera
Smart LTE Module Series
SC600Y&SC600T Hardware Design
Can be multiplexed into
differential data of the fourth
camera (negative)
Can be multiplexed into
differential data of the fourth
camera (positive)
Can be multiplexed into
differential clock of the
fourth camera (negative)
Can be multiplexed into
differential clock of the
fourth camera (positive)
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