Quectel SC600Y-EM Series Hardware Design page 37

DSI1_LN0_P 104
DSI1_LN1_N 107
DSI1_LN1_P 106
DSI1_LN2_N 109
DSI1_LN2_P 108
DSI1_LN3_N 111
DSI1_LN3_P 110
Camera Interfaces
Pin Name Pin No.
CSI0_CLK_N 89
CSI0_CLK_P 88
CSI0_LN0_N 91
CSI0_LN0_P 90
CSI0_LN1_N 93
CSI0_LN1_P 92
CSI0_LN2_N 95
CSI0_LN2_P 94
SC600Y&SC600T_Hardware_Design
data signal (negative)
LCD1 MIPI lane 0
AO
data signal (positive)
LCD1 MIPI lane 1
AO
data signal (negative)
LCD1 MIPI lane 1
AO
data signal (positive)
LCD1 MIPI lane 2
AO
data signal (negative)
LCD1 MIPI lane 2
AO
data signal (positive)
LCD1 MIPI lane 3
AO
data signal (negative)
LCD1 MIPI lane 3
AO
data signal (positive)
I/O Description
MIPI clock signal of
AI rear camera
(negative)
MIPI clock signal of
AI
rear camera (positive)
MIPI lane 0 data
AI signal of rear camera
(negative)
MIPI lane 0 data
AI signal of rear camera
(positive)
MIPI lane 1 data
AI signal of rear camera
(negative)
MIPI lane 1 data
AI signal of rear camera
(positive)
MIPI lane 2 data
AI signal of rear camera
(negative)
MIPI lane 2 data
AI signal of rear camera
(positive)
Smart LTE Module Series
SC600Y&SC600T Hardware Design
DC Characteristics Comment
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