Quectel SC600Y-EM Series Hardware Design page 39

CSI2_CLK_P 77
CSI2_LN0_N 80
CSI2_LN0_P 79
CSI2_LN1_N 82
CSI2_LN1_P 81
CSI2_LN2_N 84
CSI2_LN2_P 83
CSI2_LN3_N 86
CSI2_LN3_P 85
MCAM_MCLK 99
SCAM_MCLK 100
MCAM_RST 74
MCAM_PWDN 73
SCAM_RST 72
SCAM_PWDN 71
SC600Y&SC600T_Hardware_Design
MIPI clock signal of
AI front camera
(positive)
MIPI lane 0 data
AI signal of front camera
(negative)
MIPI lane 0 data
AI signal of front camera
(positive)
MIPI lane 1 data
AI signal of front camera
(negative)
MIPI lane 1 data
AI signal of front camera
(positive)
MIPI lane 2 data
AI signal of front camera
(negative)
MIPI lane 2 data
AI signal of front camera
(positive)
MIPI lane 3 data
AI signal of front camera
(negative)
MIPI lane 3 data
AI signal of front camera
(positive)
Master clock signal of
DO
rear camera
Master clock signal of
DO
front camera
Reset signal of rear
DO
camera
Power down signal of
DO
rear camera
Reset signal of front
DO
camera
Power down signal of
DO
front camera
Smart LTE Module Series
SC600Y&SC600T Hardware Design
V max=0.45V
OL
V min=1.35V
OH
V max=0.45V
OL
V min=1.35V
OH
V max=0.45V
OL
V min=1.35V
OH
V max=0.45V
OL
V min=1.35V
OH
V max=0.45V
OL
V min=1.35V
OH
V max=0.45V
OL
V min=1.35V
OH
1.8V power domain.
1.8V power domain.
1.8V power domain.
1.8V power domain.
1.8V power domain.
1.8V power domain.
38 / 128