Quectel SC600Y-EM Series Hardware Design page 54

Smart lte module
Table of Contents

Advertisement

The following is a reference design for USB interface:
Module
USB_ VBUS
USB_DM
USB_DP
CC1
CC2
USB_SS_TX_P
USB_SS_TX_M
USB_SS_RX_P
USB_SS_RX_M
USB_SS_ SEL
USB_OPT
In order to ensure USB performance, please follow the following principles while designing USB interface.
It is important to route the USB signal traces as differential pairs with total grounding. The impedance
of USB differential trace is 90Ω.
Pay attention to the influence of junction capacitance of ESD protection devices on USB data lines.
Typically, the capacitance value should be less than 2pF for USB 2.0 and less than 0.5pF for USB
3.0.
Do not route signal traces under crystals, oscillators, magnetic devices and RF signal traces. It is
important to route the USB differential traces in inner-layer with ground shielding on not only upper
and lower layers but also right and left sides.
Keep the ESD protection devices as close as possible to the USB connector.
Make sure the trace length difference between USB 2.0 DM/DP differential pair and that between
USB 3.0 RX/TX differential pairs both do not exceed 0.7mm.
SC600Y&SC600T_Hardware_Design
USB_VUSB
USB_DM
USB_DP
USB_ID
C1
D1
USB_OPT
R1
100nF
ESD ESD ESD
Module
1K
Figure 12: Micro USB Interface Reference Design
VDD_3V
C1
C14
R1
4.7uF
100nF
NM
Figure 13: USB Type-C Interface Reference Design
SC600Y&SC600T Hardware Design
1
VUSB
2
USB_DM
3
USB_DP
4
USB_ID
5
D2
D3
GND
C6
C2
A0+
B0+
C3
C7
A0-
B0-
C4
C8
B1+
A1+
C5
C9
A0-
B1-
C10
C0+
SEL
C0-
C11
VDD
C12
C1+
PD
C13
C1-
R1
Switch
Smart LTE Module Series
USB 3.0
VBUS_ VBUS
D-
D+
CC 1
CC2
TX2+
TX2-
RX2+
RX2-
TX1+
TX1-
RX1+
RX1-
53 / 128

Advertisement

Table of Contents
loading

Table of Contents