Quectel SC600Y-EM Series Hardware Design page 38

CSI0_LN3_N 97
CSI0_LN3_P 96
CSI1_CLK_N 184
CSI1_CLK_P 183
CSI1_LN0_N 186
CSI1_LN0_P 185
CSI1_LN1_N 188
CSI1_LN1_P 187
CSI1_LN2_N 190
CSI1_LN2_P 189
CSI1_LN3_N 192
CSI1_LN3_P 191
CSI2_CLK_N 78
SC600Y&SC600T_Hardware_Design
MIPI lane 3 data
AI signal of rear camera
(negative)
MIPI lane 3 data
AI signal of rear camera
(positive)
MIPI clock signal of
AI depth camera
(negative)
MIPI clock signal of
AI depth camera
(positive)
MIPI lane 0 data
AI signal of depth
camera (negative)
MIPI lane 0 data
AI signal of depth
camera (positive)
MIPI lane 1 data
AI signal of depth
camera (negative)
MIPI lane 1 data
AI signal of depth
camera (positive)
MIPI lane 2 data
AI signal of depth
camera (negative)
MIPI lane 2 data
AI signal of depth
camera (positive)
MIPI lane 3 data
AI signal of depth
camera (negative)
MIPI lane 3 data
AI signal of depth
camera (positive)
MIPI clock signal of
AI front camera
(negative)
Smart LTE Module Series
SC600Y&SC600T Hardware Design
Can be multiplexed
into differential data
of the fourth camera
(negative).
Can be multiplexed
into differential data
of the fourth camera
(positive).
Can be multiplexed
into differential clock
of the fourth camera
(negative).
Can be multiplexed
into differential clock
of the fourth camera
(positive).
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