Quectel SC600Y-EM Series Hardware Design page 36

LCD_BL_K3 24
LCD_BL_K4 25
PMU_MPP4 152
LCD0_RST 127
LCD0_TE 126
LCD1_RST 113
LCD1_TE 114
DSI0_CLK_N 116
DSI0_CLK_P 115
DSI0_LN0_N 118
DSI0_LN0_P 117
DSI0_LN1_N 120
DSI0_LN1_P 119
DSI0_LN2_N 122
DSI0_LN2_P 121
DSI0_LN3_N 124
DSI0_LN3_P 123
DSI1_CLK_N 103
DSI1_CLK_P 102
DSI1_LN0_N 105
SC600Y&SC600T_Hardware_Design
Current sink for LCD
AI
backlight
Current sink for LCD
AI
backlight
DO PWM signal output
DO LCD0 reset signal
LCD0 tearing effect
DI
signal
DO LCD1 reset signal
LCD1 tearing effect
DI
signal
LCD0 MIPI clock
AO
signal (negative)
LCD0 MIPI clock
AO
signal (positive)
LCD0 MIPI lane 0
AO
data signal (negative)
LCD0 MIPI lane 0
AO
data signal (positive)
LCD0 MIPI lane 1
AO
data signal (negative)
LCD0 MIPI lane 1
AO
data signal (positive)
LCD0 MIPI lane 2
AO
data signal (negative)
LCD0 MIPI lane 2
AO
data signal (positive)
LCD0 MIPI lane 3
AO
data signal (negative)
LCD0 MIPI lane 3
AO
data signal (positive)
LCD1 MIPI clock
AO
signal (negative)
LCD1 MIPI clock
AO
signal (positive)
AO LCD1 MIPI lane 0
Smart LTE Module Series
SC600Y&SC600T Hardware Design
V max=0.45V
OL
V min=1.35V
OH
V max=0.63V
IL
V min=1.17V
IH
V max=0.45V
OL
V min=1.35V
OH
V max=0.63V
IL
V min=1.17V
IH
1.8V power domain.
Active low.
1.8V power domain.
1.8V power domain.
Active low.
1.8V power domain.
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