Analog Devices ADSP-21369 EZ-KIT Lite Manual page 28

External Memory
Table 1-1 provides start and end addresses of the on-board external
memories.
Table 1-1. EZ-KIT Lite Evaluation Board External Memory
Start Address End Address
0x0020 0000 0x0027 FFFF
0x0400 0000 0x040F FFFF
0x0800 0000 0x083F 0000
0x0C00 0000 0x0CFF FFFF
0x0C00 0000 0x0FFF FFFF
Parallel flash memory, SDRAM, and SRAM are connected to the external
memory of the processor. To access SRAM and flash memories, use mem-
ory addressing via the respective memory bank or use the DMA controller.
SDRAM memory is connected to the SDRAM controller of the processor.
A set of programmable timing parameters is available to configure the
SDRAM banks to support slower memory accesses. Care must be taken
when configuring the SDRAM control registers. For more information
regarding the setup of the SDRAM controller, refer to the ADSP-21368
SHARC Processor Hardware Reference (includes ADSP-21369).
An example program is included in the EZ-KIT Lite installation directory
to demonstrate the controller setup.
SPI flash memory is connected to the SPI port of the processor; SPI flash
designates:
• DPI pin 5 (
• DPI pin 3 (
• DPI pin 1 (
• DPI pin 2 (
1-8
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Content
SRAM memory (
Flash memory (
SDRAM memory (
Unused chip select (
Unused chip select (
) as a chip select
DPI5
) as the SPI clock
DPI3
) as the
DPI1 MOSI
) as the
DPI2 MISO
ADSP-21369 EZ-KIT Lite Evaluation System Manual
)
~MS0
)
~MS1
)
~MS2
) for non-SDRAM addresses
~MS3
) for SDRAM addresses
~MS3