Figure 29. Maximum Dynamic Current Consumption On V - STMicroelectronics STM32L151QCH6 Manual

Electrical characteristics

Figure 29. Maximum dynamic current consumption on V

ADC clock
I
700µA
300µA
Ts
Multiplexed channels
(µs)
2.4 V < V < 3.6 V 1.8 V < V
DDA
0.25 Not allowed
0.5625 0.8
1 2.0
1.5 3.0
3 6.8
6 15.0
12 32.0
24 50.0
1. Guaranteed by design, not tested in production.
2. Number of samples calculated for f
with respect to the minimum sampling time Ts (µs),
General PCB design guidelines
Power supply decoupling should be performed as shown in
procedure depends on whether V
should be ceramic (good quality). They should be placed as close as possible to the chip.
106/133
Sampling (n cycles)
ref+
Table 57. Maximum source impedance R
R
AIN
< 2.4 V 2.4 V < V
DDA
Not allowed
Not allowed
0.8
1.8
4.0
10.0
25.0
50.0
= 16 MHz. For f
ADC
STM32L151xC/C-A STM32L152xC/C-A
conversion
Conversion (12 cycles)
max (kΩ)
Direct channels
< 3.6 V 1.8 V < V
DDA
0.7
2.0
4.0
6.0
15.0
30.0
50.0
50.0
= 8 and 4 MHz the number of sampling cycles can be reduced
ADC
is connected to V
REF+
DocID026119 Rev 5
supply pin during ADC
REF+
(1)
max
AIN
f
ADC
< 2.4 V
DDA
Not allowed
1.0
3.0
4.5
10.0
20.0
40.0
50.0
Figure 11. The applicable
or not. The 100 nF capacitors
DDA
MS36686V1
Ts (cycles)
(2)
= 16 MHz
4
9
16
24
48
96
192
384