Figure 25. I 2 S Slave Timing Diagram (Philips Protocol); Figure 26. I 2 S Master Timing Diagram (Philips Protocol) - STMicroelectronics STM32L151QCH6 Manual

STM32L151xC/C-A STM32L152xC/C-A
ODD bit value, digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max of
(I2SDIV+ODD)/(2*I2SDIV+ODD). Fs max is supported for each mode/condition.
1. Measurement points are done at CMOS levels: 0.3 × V
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
1. Guaranteed by characterization results, not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
2
Figure 25. I S slave timing diagram (Philips protocol)
2
Figure 26. I S master timing diagram (Philips protocol)
DocID026119 Rev 5
Electrical characteristics
and 0.7 × V .
DD DD
(1)
(1)
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