VersaLogic Ocelot Reference Manual page 63

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Datasheet of VL-CBR-2012 - 20" 24-BIT LVDS CABLE
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PC104_IRQ_EN1 (Read/Write) 1DFh
D7 D6
16BIT_EN MEM_EN3
Bit Mnemonic
D7 16BIT_EN
D6 MEM_EN3
D5 MEM_EN2
D4 MEM_EN1
D3 MEM_EN0
D2 Reserved
D1 IRQ15_EN
D0 IRQ12_EN
VL-EPMs-21 Reference Manual
D5 D4
MEM_EN2 MEM_EN1
Table 30: PC/104 Interrupt Request Register 1 Bit Assignments
Description
PC/104 16 bit I/O cycle enable – This bit controls 16bit I/O cycles on the PC/104
bus. When enabled, the bridge expects two consecutive 8-bit cycles from the LPC
bus before forwarding the data to the PC/104 bus as a single 16-bit cycle.
0 = all I/O cycles are 8-bit on PC/104 bus
1 = 16-bit I/O cycles enabled on PC/104 bus
ISA Memory Access – 16 KB ISA memory window 0x000DC000 to
0x000DFFFF forwarded to 0xFFD0C000 to 0xFFD0FFFF.
0 = disable on PC/104 bus
1 = enable on PC/104 bus
ISA Memory Access – 16 KB ISA memory window 0x000D8000 to 0x000DBFFF
forwarded to 0xFFD08000 to 0xFFD0BFFF.
0 = disable on PC/104 bus
1 = enable on PC/104 bus
ISA Memory Access – 16 KB ISA memory window 0x000D4000 to 0x000D7FFF
forwarded to 0xFFD04000 to 0xFFD07FFF.
0 = disable on PC/104 bus
1 = enable on PC/104 bus
ISA Memory Access – 16 KB ISA memory window 0x000D0000 to 0x000D3FFF
forwarded to 0xFFD00000 to 0xFFD03FFF.
0 = disable on PC/104 bus
1 = enable on PC/104 bus
These bits have no function.
PC/104 IRQ15 enable
0 = disabled on PC/104 bus
1 = enabled on PC/104 bus
PC/104 IRQ12 enable
0 = disabled on PC/104 bus
1 = enabled on PC/104 bus
D3 D2
MEM_EN0 Reserved IRQ15_EN
Special Registers
D1 D0
IRQ12_EN
56