Watchdog Timer - VersaLogic Ocelot Reference Manual

Distributor of VersaLogic Corporation: Excellent Integrated System Limited
Datasheet of VL-CBR-2012 - 20" 24-BIT LVDS CABLE
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Watchdog Timer

A watchdog timer can be implemented using the VL-EPMs-21 WDT register and the SMSC
SCH3114 Super I/O chip. The BIOS initializes the SCH3114 WDT registers during post.
See the SCH311X Datasheet
1. Configure PLD Watchdog control bits (0x1D3.5:4). Examples:
a. 0x1D3 POR default = 00h
b. 0x1D3 = 00h = Do Nothing
c. 0x1D3 = 10h = Cold Reset
d. 0x1D3 = 20h = Power Cycle (3 sec. off time)
e. 0x1D3 = 30h = Power Off
2. Configure Super I/O WDT (GP60) pin (0x0C47.7,3:0). Examples:
a. 0x0C47 POR default = 0Eh
b. 0x0C47 = 0Eh = WDT enable, Push-Pull, Inverted
3. Configure Timescale (0x0C65.7). Examples:
a. 0x0C65 POR default = 08h
b. 0x0C65 = 00h = Minutes
c. 0x0C65 = 80h = Seconds
4. Configure Timeout value (0x0C66.7:0). Examples:
a. 0x0C66 POR default = 00h
b. 0x0C66 = 00h = WDT disabled
c. 0x0C66 = 01h to FFh = Timeout value + 1 (min./sec.)
5. (optional) Read SIO WDT status bit (0x0C68.1). Examples:
a. 0x0C68 POR default = 00h
b. 0x0C68 = 00h = timer counting
c. 0x0C68 = 01h = timeout occurred (Note: Bit 0 is not automatically cleared by
PCI reset but can be reset by software.)
6. (optional) Read PLD WDT status bit (0x1D3.7). Examples:
a. 0x1D3 POR default = 00h
b. 0x1D3 = 00h = No timeout has occurred
c. 0x1D3 = 80h = timeout has occurred
7. (optional) "Feeding" the watchdog.
a. Repeat step 4
VL-EPMs-21 Reference Manual
for detailed Super I/O chip information.
System Features
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