VersaLogic Ocelot Reference Manual page 51

Distributor of VersaLogic Corporation: Excellent Integrated System Limited
Datasheet of VL-CBR-2012 - 20" 24-BIT LVDS CABLE
Contact us: sales@integrated-circuit.com Website: www.integrated-circuit.com
SPISTATUS (READ/WRITE) 1D9h
D7
IRQSEL1 IRQSEL0
Bit Mnemonic
D7-D6 IRQSEL
D5-D4 SPICLK
D3 HW_IRQ_EN
D2 LSBIT_1ST
D1 HW_INT
D0 BUSY
VL-EPMs-21 Reference Manual
D6 D5 D4
SPICLK1 SPICLK0
Table 18: SPI Control Register Assignments
Description
IRQ Select – These bits select which IRQ will be asserted when a hardware
interrupt from a connected SPI device occurs. The HW_IRQ_EN bit must be
set to enable SPI IRQ functionality.
IRQSEL1 IRQSEL0
0 0
0 1
1 0
1 1
SPI SCLK Frequency – These bits set the SPI clock frequency.
SPICLK1 SPICLK0
0 0
0 1
1 0
1 1
Hardware IRQ Enable – Enables or disables the use of the selected IRQ
(IRQSEL) by an SPI device.
0 = SPI IRQ disabled, default
1 = SPI IRQ enabled
Note: When an IRQ is enabled for the SPX bus, it has priority over the PC/104
bus. For example, if IRQ5 is routed to the PC/104 bus and enabled for the SPX
bus, it will not be available to the PC/104 bus.
SPI Shift Direction – Controls the SPI shift direction of the SPIDATA registers.
The direction can be shifted toward the least significant bit or the most
significant bit.
0 = SPIDATA data is left-shifted (MSbit first), default
1 = SPIDATA data is right-shifted (LSbit first)
SPI Device Interrupt State – This bit is a status flag that indicates when the
hardware SPX signal SINT# is asserted.
0 = Hardware interrupt on SINT# is deasserted
1 = Interrupt is present on SINT#
This bit is read-only and is cleared when the SPI device's interrupt is cleared.
SPI Busy Flag – This bit is a status flag that indicates when an SPI
transaction is underway.
0 = SPI bus idle
1 = SCLK is clocking data in and out of the SPIDATA registers
This bit is read-only.
D3 D2
HW_IRQ_EN LSBIT_1ST
IRQ
IRQ3
IRQ4
IRQ5
IRQ10
Frequency
1.042 MHz
2.083 MHz
4.167 MHz
8.333 MHz
Interfaces and Connectors
D1 D0
HW_INT BUSY
44