Furuno FELCOM 15 Service Manual page 32

2.3 Terminal unit, IC-215
Frequency control
For example, when the receiving frequency from the satellite differs from the carrier
frequency input to the de-modulating circuit, the error rate is increased.
CPU detects the frequency difference and the phase difference of I signal and Q signal. The
detection data controls the frequency of the TX/RX PLL synthesizer oscillator (TCXO:
16.8 MHz) so that the output frequency is equal to the receiving frequency by controlling
the PLL synthesizer output frequency.
The standard oscillator, 16.8 MHz is controlled by the 1 kHz step at the first FFT.
Fig.2.3.5 shows the block diagram of the RF CON/CPU receiving frequency control.
The frequency complemented value is checked at "REF Offset Freq" in Status display.
"OK" appears when the Offset Freq. is less than 150 Hz.
Fig.2.3.5 Block diagram of RF CON/CPU receiving frequency control
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