Mitsubishi M16C/60 Series Software Manual
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Mitsubishi M16C/60 Series Software Manual

Mitsubishi M16C/60 Series Software Manual

16-bit single-chip microcomputer
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ADVANCED AND EVER ADVANCING
MITSUBISHI ELECTRIC
MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER
740 FAMILY
740
Family
Software Manual
MITSUBISHI
ELECTRIC

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  • Page 1 ADVANCED AND EVER ADVANCING MITSUBISHI ELECTRIC MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY Family Software Manual MITSUBISHI ELECTRIC...
  • Page 2 Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product...
  • Page 3 REVISION DESCRIPTION LIST 740 Family Software Manual Rev. Rev. Revision Description date First Edition 970829 (1/1)
  • Page 4 Preface This software manual is for users of the 740 Family. Register structures, addressing modes and instructions are introduced in each section. The enhanced instruction set with enhanced data and memory operations enable efficient programming. Please refer to the “USER’S MANUAL” appropriate for the hardware device or the development support tools used.

  • Page 5: Table Of Contents

    Table of contents Table of contents CHAPTER 1. OVERVIEW .................... 1 CHAPTER 2. CENTRAL PROCESSING UNIT (CPU) ..........2 2.1 Accumulator (A) ........................2 2.2 Index Register X (X), Index Register Y (Y) ................ 2 2.3 Stack Pointer (S) ........................3 2.4 Program Counter (PC) ......................
  • Page 6 Table of contents <Addressing Mode> Immediate ........7 Special Page ......21 Accumulator ......8 Zero Page Bit ......22 Zero Page ......... 9 Accumulator Bit ...... 23 Zero Page X ......10 Accumulator Bit Relatibe ..24 Zero Page Y ......11 Zero Page Bit Relative ..

  • Page 7: Chapter 1. Overview

    OV ERV IEW 1. OVERVIEW The distinctive features of the CMOS 8-bit microcomputers 740 Family’s software are described below: 1) An efficient instruction set and many addressing modes allow the effective use of ROM. 2) The same bit management, test, and branch instructions can be performed on the Accu- mulator, memory, or I/O area.

  • Page 8: Chapter 2. Central Processing Unit (Cpu)

    C EN TRAL PROC ESSIN G UN IT Accumulator (A) Index Register X (X), Index Register Y (Y) 2. CENTRAL PROCESSING UNIT (CPU) Six main registers are built into the CPU of the 740 Family. The Program Counter (PC) is a sixteen-bit register; however, the Accumulator (A), Index Register X (X), Index Register Y (Y), Stack Pointer (S) and Processor Status Register (PS) are eight-bit registers.

  • Page 9: Stack Pointer (S)

    CENTRAL PROCESSING UNIT Stack Pointer (S) 2.3 Stack Pointer (S) The Stack Pointer is an eight-bit register used for generating interrupts and calling subroutines. When an interrupt is received, the following procedure is performed automatically in the indicated sequence: (1) The contents of the high-order eight bits of the Program Counter (PC ) are saved to an address using the Stack Pointer contents for the low-order eight bits of the address.

  • Page 10: Program Counter (Pc)

    C EN TRAL PROC ESSIN G UN IT Program Counter (PC) Processor Status Register (PS) 2.4 Program Counter (PC) The Program Counter is a sixteen-bit counter consisting of PC and PC , which are each eight-bit registers. The contetnts of the Program Counter indicates the address which an instruction to be executed next is stored.
  • Page 11 C EN TRAL PROC ESSIN G UN IT Processor Status Register (PS) [ X modified operation mode flag T ] ----------------------- Bit 5 This flag determines whether arithmetic operations are performed via the Accumulator or directly on a memory location. When the flag is set to “0”, arithmetic operations are performed between the Accumulator and memory.

  • Page 12: Chapter 3. Instructions

    IN STRUC TION S Addressing mode 3. INSTRUCTIONS 3.1 Addressing Mode The 740 Family has 19 addressing modes and a powerful memory access capability. When extracting data required for arithmetic and logic operations from memory or when storing the results of such operations in memory, a memory address must be specified. The specification of the memory address is called addressing.
  • Page 13 IN STRUC TION S Im m e d ia t e Addressing mode Ad d r e s s in g m o d e : Immediate F u n c tio n : Specifies the Operand as the data for the instruction. In s tr u c tio n s : ADC, AND, CMP, CPX, CPY, EOR, LDA, LDX, LDY, ORA, SBC...
  • Page 14 IN STRUC TION S Ac c u m u la t o r Addressing mode Ad d r e s s in g m o d e : Accumulator F u n c tio n : Specifies the contents of the Accumulator as the data for the instruction.
  • Page 15 IN STRUC TION S Ze r o Pa g e Addressing mode Ad d r e s s in g m o d e : Zero Page Specifies the contents in a Zero Page memory F u n c tio n : location as the data for the instruction.
  • Page 16 IN STRUC TION S Ze r o Pa g e X Addressing mode Ad d r e s s in g m o d e : Zero Page X F u n c tio n : Specified the contents in a Zero Page memory location as the data for the instruction.
  • Page 17 IN STRUC TION S Ze r o Pa g e Y Addressing mode Ad d r e s s in g m o d e : Zero Page Y F u n c tio n : Specifies the contents in a Zero Page memory location as the data for the instruction.
  • Page 18 IN STRUC TION S Ab s o lu t e Addressing mode Ad d r e s s in g m o d e : Absolute F u n c tio n : Specifies the contents in a memory location as the data for the instruction.
  • Page 19 IN STRUC TION S Ab s o lu t e X Addressing mode Ad d r e s s in g m o d e : Absolute X F u n c tio n : Specifies the contents in a memory location as the data for the instruction.
  • Page 20 IN STRUC TION S Ab s o lu t e Y Addressing mode Ad d r e s s in g m o d e : Absolute Y F u n c tio n : Specifies the contents in a memory location as the data for the instruction.
  • Page 21 IN STRUC TION S Im p lie d Addressing mode Ad d r e s s in g m o d e : Implied F u n c tio n : Operates on a given register or the Accumulator, but the address is always inherent in the instruction.
  • Page 22 IN STRUC TION S Re la t iv e Addressing mode Ad d r e s s in g m o d e : Relative F u n c tio n : Specifies the address in a memory location where the next Op-Code is located.
  • Page 23 IN STRUC TION S In d ir e c t X Addressing mode Ad d r e s s in g m o d e : Indirect X F u n c tio n : Specifies the contents in a memory location as the data for the instruction.
  • Page 24 IN STRUC TION S In d ir e c t Y Addressing mode Ad d r e s s in g m o d e : Indirect Y F u n c tio n : Specifies the contents in a memory location as the data for the instruction.
  • Page 25 IN STRUC TION S In d ir e c t Ab s o lu t e Addressing mode Ad d r e s s in g m o d e : Indirect Absolute F u n c tio n : Specifies the address in a memory location as the jump destination address.
  • Page 26 IN STRUC TION S Ze r o Pa g e In d ir e c t Addressing mode Ad d r e s s in g m o d e : Zero Page Indirect Absolute F u n c tio n : Specifies the address in a memory location as the jump destination address.
  • Page 27 IN STRUC TION S Sp e c ia l Pa g e Addressing mode Ad d r e s s in g m o d e : Special Page F u n c tio n : Specifies the address in a Special Page memory location as the jump destination address.
  • Page 28 IN STRUC TION S Ze r o Pa g e Bit Addressing mode Ad d r e s s in g m o d e : Zero Page Bit F u n c tio n : Specifies one bit of the contents in a Zero Page memory location as the data for the instruction.
  • Page 29 IN STRUC TION S Ac c u m u la t o r Bit Addressing mode Ad d r e s s in g m o d e : Accumulator Bit F u n c tio n : Specifies one bit of the Accumulator as the data for the instruction.
  • Page 30 IN STRUC TION S Ac c u m u la t o r Bit Re la t iv e Addressing mode Ad d r e s s in g m o d e : Accumulator Bit Relative F u n c tio n : Specifies the address in a memory location where the next Op-Code is located.
  • Page 31 IN STRUC TION S Ze r o Pa g e Bit Re la t iv e Addressing mode Ad d r e s s in g m o d e : Zero Page Bit Relative F u n c tio n : Specifies the address of a memory location where the next Op-Code is located.

  • Page 32: Instruction Set

    IN STRUC TION S Instruction Set 3.2 Instruction Set The 740 Family has 71 types of instructions. The detailed explanation of the instructions is presented in §3.3. Note that some instructions cannot be used for any products. 3.2.1 Data transfer instructions These instructions transfer the data between registers, register and memory, and memories.

  • Page 33: Operating Instruction

    IN STRUC TION S Instruction Set 3.2.2 Operating instruction The operating instructions include the operations of addition and subtraction, logic, comparison, rotation, and shift. The operating instructions are as follows: Contents Instructions Add memory contents and C flag to Accumulator or memory where is indicated by Index Register X Subtracts memory contents and C flag’s complement from Accumulator or memory where is indicated by Index...

  • Page 34: Bit Managing Instructions

    IN STRUC TION S Instruction Set 3.2.3 Bit managing instructions The bit managing instructions clear “0” or set “1” designated bits of the Accumulator or memory. Contents Instructions Clear designated bit in the Accumulator or memory Set designated bit in the Accumulator or memory Managing 3.2.4 Flag setting instructions The flag setting instructions clear “0”...

  • Page 35: Interrupt Instruction (Break Instruction)

    IN STRUC TION S Instruction Set 3.2.6 Interrupt instruction (Break instruction) This instruction causes a software interrupt. Contents Instruction Interrupt Executes a software interrupt. 3.2.7 Special instructions These special instructions control the oscillation and the internal clock. Contents Instructions Stops the internal clock. Special Stops the oscillation of oscillator.

  • Page 36: Description Of Instructions

    IN STRUC TION S Instruction Set 3.3 Description of instructions This section presents in detail the 740 Family instructions by arranging mnemonics of instruc- tions alphabetically and dividing each instruction essentially into one page. The heading of each page is a mnemonic. Operation, explanation and changes of status flags are indicated for each instruction.
  • Page 37 AD C AD C D WITH ARRY When (T) = 0, (A) ← (A) + (M) + (C) Op e r a t io n : (T) = 1, (M(X)) ← (M(X)) + (M) + (C) F u n c t io n : When T = 0, this instruction adds the contents M, C, and A;...
  • Page 38 AN D AN D LOGICAL When (T) = 0, (A) ← (A) ∧ (M) Op e r a t io n : (T) = 1, (M(X)) ← (M(X)) ∧ (M) When T = 0, this instruction transfers the contents of A and M F u n c t io n : to the ALU which performs a bit-wise AND operation and stores the result back in A.
  • Page 39 RITHMETIC HIFT Op e r a t io n : ← ← F u n c t io n : This instruction shifts the content of A or M by one bit to the left, with bit 0 always being set to 0 and bit 7 of A or M always being contained in C.
  • Page 40 RANCH ON LEAR When (Mi) or (Ai) = 0, (PC) ← (PC) + n + REL Op e r a t io n : (Mi) or (Ai) = 1, (PC) ← (PC) + n n: If addressing mode is Zero Page Bit Relative, n=3. And if addressing mode is Accumulator Bit Relative, n=2.
  • Page 41 RANCH ON When (Mi) or (Ai) = 1, (PC) ← (PC) + n + REL Op e r a t io n : (Mi) or (Ai) = 0, (PC) ← (PC) + n n : If addressing mode is Zero Page Bit Relative, n=3. And if addressing mode is Accumulator Bit Relative, n=2.
  • Page 42 BC C BC C RANCH ON ARRY LEAR When (C) = 0, (PC) ← (PC) + 2 + REL Op e r a t io n : (C) = 1, (PC) ← (PC) + 2 F u n c t io n : This instruction takes a branch to the appointed address if C is 0.
  • Page 43 BC S BC S RANCH ON ARRY When (C) = 1, (PC) ← (PC) + 2 + REL Op e r a t io n : (C) = 0, (PC) ← (PC) + 2 F u n c t io n : This instruction takes a branch to the appointed address if C is 1.
  • Page 44 RANCH ON QUAL When (Z) = 1, (PC) ← (PC) + 2 + REL Op e r a t io n : (Z) = 0, (PC) ← (PC) + 2 F u n c t io n : This instruction takes a branch to the appointed address when Z is 1.
  • Page 45 TEST IN MEMORY WITH ACCUMULATOR (A) ∧ (M) Op e r a t io n : F u n c t io n : This instruction takes a bit-wise logical AND of A and M contents; however, the contents of A and M are not modified. The contents of N, V, Z are changed, but the contents of A, M remain unchanged.
  • Page 46 BM I BM I RANCH ON RESULT When (N) = 1, (PC) ← (PC) + 2 + REL Op e r a t io n : (N) = 0, (PC) ← (PC) + 2 F u n c t io n : This instruction takes a branch to the appointed address when N is 1.
  • Page 47 BN E BN E RANCH ON QUAL When (Z) = 0, (PC) ← (PC) + 2 + REL Op e r a t io n : (Z) = 1, (PC) ← (PC) + 2 F u n c t io n : This instruction takes a branch to the appointed address if Z is 0.
  • Page 48 RANCH ON RESULT When (N) = 0, (PC) ← (PC) + 2 + REL Op e r a t io n : (N) = 1, (PC) ← (PC) + 2 F u n c t io n : This instruction takes a branch to the appointed address if N is 0.
  • Page 49 ANCH LWAYS (PC) ← (PC) + 2 + REL Op e r a t io n : F u n c t io n : This instruction branches to the appointed address. The branch address is specified by a relative address. St a t u s fla g : No change Addressing mode...
  • Page 50 FORCE (B) ← 1 Op e r a t io n : (PC) ← (PC) + 2 (M(S)) ← (PC (S) ← (S) – 1 (M(S)) ← (PC (S) ← (S) – 1 (M(S)) ← (PS) (S) ← (S) – 1 (I) ←...
  • Page 51 BV C BV C RANCH ON O ERFLOW LEAR When (V) = 0, (PC) ← (PC) + 2 + REL Op e r a t io n : (V) = 1, (PC) ← (PC) + 2 F u n c t io n : This instruction takes a branch to the appointed address if V is 0.
  • Page 52 BV S BV S RANCH ON O ERFLOW When (V) = 1, (PC) ← (PC) + 2 + REL Op e r a t io n : (V) = 0, (PC) ← (PC) + 2 F u n c t io n : This instruction takes a branch to the appointed address when V is 1.
  • Page 53 C LB C LB (Ai) ← 0, or Op e r a t io n : (Mi) ← 0 F u n c t io n : This instruction clears the designated bit i of A or M. St a t u s fla g : No change Statement Machine codes...
  • Page 54 C LC C LC ARRY FLAG (C) ← 0 Op e r a t io n : F u n c t io n : This instruction clears C. St a t u s fla g : N : No change No change No change No change...
  • Page 55 C LD C LD ECIMAL MODE (D) ← 0 Op e r a t io n : This instruction clears D. F u n c t io n : St a t u s fla g : No change No change No change No change No change...
  • Page 56 C LI C LI NTERRUPT DISABLE STATUS (I) ← 0 Operation : Function : This instruction clears I. Status flag: N : No change No change No change No change No change No change No change Addressing mode Statement Machine codes Byte number Cycle number ∆CLI...
  • Page 57 C LT C LT RANSFER FLAG (T) ← 0 Op e r a t io n : F u n c t io n : This instruction clears T. St a t u s fla g : No change No change No change No change No change...
  • Page 58 C LV C LV EAR O ERFLOW FLAG (V) ← 0 Op e r a t io n : This instruction clears V. F u n c t io n : No change St a t u s fla g No change No change No change...
  • Page 59 C M P C M P Op e r a t io n : When (T) = 0, (A) – (M) (T) = 1, (M(X)) – (M) F u n c t io n : When T = 0, this instruction subtracts the contents of M from the contents of A.
  • Page 60 C OM C OM PLEMENT (M) ← (M) Op e r a t io n : F u n c t io n : This instruction takes the one’s complement of the contents of M and stores the result in M. St a t u s fla g : N is 1 when bit 7 of the M is 1 after the operation;...
  • Page 61 C PX C PX ARE MEMORY AND INDEX REGISTER Op e r a t io n : (X) – (M) F u n c t io n : This instruction subtracts the contents of M from the contents of X. The result is not stored and the contents of X and M are not modified.
  • Page 62 C PY C PY ARE MEMORY AND INDEX REGISTER (Y) – (M) Op e r a t io n : This instruction subtracts the contents of M from the contents of F u n c t io n : Y. The result is not stored and the contents of Y and M are not modified.
  • Page 63 D EC D EC REMENT BY ONE (A) ← (A) – 1, or Op e r a t io n : (M) ← (M) – 1 F u n c t io n : This instruction subtracts 1 from the contents of A or M. St a t u s fla g : N is 1 when bit 7 is 1 after the addition;...
  • Page 64 D EX D EX CREMENT INDEX REGISTER BY ONE (X) ← (X) – 1 Op e r a t io n : F u n c t io n : This instruction subtracts one from the current contents of X. St a t u s fla g : N : N is 1 when bit 7 is 1 after the operation;...
  • Page 65 D EY D EY CREMENT INDEX REGISTER BY ONE (Y) ← (Y) – 1 Op e r a t io n : F u n c t io n : This instruction subtracts one from the current contents of Y. St a t u s fla g : N : N is 1 when bit 7 is 1 after the operation;...
  • Page 66 D IV D IV IDE MEMORY BY ACCUMULATOR (A) ← (M(zz+(X)+1),M(zz+(X)) / (A) Op e r a t io n : M(S) ← one’s complement of Remainder (S) ← (S) – 1 F u n c t io n : Divides the 16-bit data in M(zz+(X)) (low-order byte) and M(zz+(X)+1) (high-order byte) by the contents of A.
  • Page 67 XCLUSIVE MEMORY WITH ACCUMULATOR When (T) = 0, (A) ← (A) ∀ (M) Op e r a t io n : (T) = 1, (M(X)) ← (M(X)) ∀ (M) F u n c t io n : When T = 0, this instruction transfers the contents of the M and A to the ALU which performs a bit-wise Exclusive OR, and stores the result in A.
  • Page 68 IN C IN C REMENT BY ONE (A) ← (A) + 1, or Op e r a t io n : (M) ← (M) + 1 F u n c t io n : This instruction adds one to the contents of A or M. St a t u s fla g : N : N is 1 when bit 7 is 1 after the operation;...
  • Page 69 IN X IN X CREMENT INDEX REGISTER BY ONE (X) ← (X) + 1 Op e r a t io n : F u n c t io n : This instruction adds one to the contents of X. St a t u s fla g : N is 1 when bit 7 is 1 after the operation;...
  • Page 70 IN Y IN Y CREMENT INDEX REGISTER BY ONE (Y) ← (Y) + 1 Op e r a t io n : F u n c t io n : This instruction adds one to the contents of Y. St a t u s fla g : N is 1 when bit 7 is 1 after the operation;...
  • Page 71 J M P J M P Op e r a t io n : When addressing mode is (a) Absolute, then (PC) ← hhll (b) Indirect Absolute, then ) ← (hhll) ) ← (hhll+1) (c) Zero page Indirect Absolute, then ) ←...
  • Page 72 J SR J SR UMP TO OUTINE (M(S)) ← (PC Op e r a t io n : (S) ← (S) – 1 (M(S)) ← (PC (S) ← (S) – 1 After the above operations, if the addressing mode is (a) Absolute, then (PC) ←...
  • Page 73 LD A LD A CCUMULATOR WITH MEMORY When (T) = 0, (A) ← (M) Op e r a t io n : (T) = 1, (M(X)) ← (M) F u n c t io n : When T = 0, this instruction transfers the contents of M to A. When T = 1, this instruction transfers the contents of M to (M(X)).
  • Page 74 LD M LD M OAD IMMEDIATE ATA TO EMORY (M) ← nn Op e r a t io n : F u n c t io n : This instruction loads the immediate value in M. St a t u s fla g : No change Addressing mode Statement...
  • Page 75 LD X LD X INDEX REGISTER FROM MEMORY (X) ← (M) Op e r a t io n : F u n c t io n : This instruction loads the contents of M in X. St a t u s fla g : N : N is 1 when bit 7 is 1 after the operation;...
  • Page 76 LD Y LD Y INDEX REGISTER FROM MEMORY (Y) ← (M) Op e r a t io n : F u n c t io n : This instruction loads the contents of M in Y. St a t u s fla g : N : N is 1 when bit 7 is 1 after the operation;...
  • Page 77 OGICAL HIFT IGHT Op e r a t io n : → → F u n c t io n : This instruction shifts either A or M one bit to the right such that bit 7 of the result always is set to 0, and the bit 0 is stored in C.
  • Page 78 M UL M UL TIPLY ACCUMULATOR AND MEMORY M(S) • (A) ← (A) Op e r a t io n : M(zz+(X)) (S) ← (S) – 1 F u n c t io n : Multiplies Accumulator with the memory specified by the Zero Page X addressing mode and stores the high-order byte of the result on the Stack and the low-order byte in A.
  • Page 79 N OP N OP ERATION (PC) ← (PC) + 1 Op e r a t io n : F u n c t io n : This instruction adds one to the PC but does no other operation. St a t u s fla g : No change Machine codes Byte number...
  • Page 80 MEMORY WITH CCUMULATOR When (T) = 0, (A) ← (A) ∨ (M) Op e r a t io n : (T) = 1, (M(X)) ← (M(X)) ∨ (M) F u n c t io n : When T = 0, this instruction transfers the contents of A and M to the ALU which performs a bit-wise “OR”, and stores the result in A.
  • Page 81 PH A PH A CCUMULATOR ON STACK (M(S)) ← (A) Op e r a t io n : (S) ← (S) – 1 F u n c t io n : This instruction pushes the contents of A to the memory location designated by S, and decrements the contents of S by one.
  • Page 82 PH P PH P ROCESSOR STATUS ON STACK (M(S)) ← (PS) Op e r a t io n : (S) ← (S) – 1 F u n c t io n : This instruction pushes the contents of PS to the memory loca- tion designated by S and decrements the contents of S by one.
  • Page 83 CCUMULATOR FROM STACK (S) ← (S) + 1 Op e r a t io n : (A) ← (M(S)) F u n c t io n : This instruction increments S by one and stores the contents of the memory designated by S in A. St a t u s fla g : N is 1 when bit 7 is 1 after the operation ;...
  • Page 84 ROCESSOR STATUS FROM STACK (S) ← (S) + 1 Op e r a t io n : (PS) ← (M(S)) F u n c t io n : This instruction increments S by one and stores the contents of the memory location designated by S in PS. St a t u s fla g : Value returns to the original one that was pushed in the stack.
  • Page 85 OTATE NE BIT Op e r a t io n : F u n c t io n : This instruction shifts either A or M one bit left through C. C is stored in bit 0 and bit 7 is stored in C. St a t u s fla g : N is 1 when bit 6 is 1 before the operation;...
  • Page 86 OTATE NE BIT IGHT Op e r a t io n : F u n c t io n : This instruction shifts either A or M one bit right through C. C is stored in bit 7 and bit 0 is stored in C. St a t u s fla g : N is 1 when C is 1 before the operation;...
  • Page 87 OTATE IGHT OF OUR BITS Op e r a t io n : F u n c t io n : This instruction rotates 4 bits of the M content to the right. St a t u s fla g : No change Addressing mode Statement...
  • Page 88 URN FROM NTERRUPT (S) ← (S) + 1 Op e r a t io n : (PS) ← (M(S)) (S) ← (S) + 1 ) ← (M(S)) (S) ← (S) + 1 ) ← (M(S)) F u n c t io n : This instruction increments S by one, and stores the contents of the memory location designated by S in PS.
  • Page 89 URN FROM UBROUTINE ) ← (M(S)) Op e r a t io n : (S) ← (S) + 1 ) ← (M(S)) (PC) ← (PC) + 1 F u n c t io n : This instruction increments S by one and stores the contents of the memory location designated by S in PC .
  • Page 90 TRACT WITH ARRY When (T) = 0, (A) ← (A) – (M) – (C) Op e r a t io n : (T) = 1, (M(X)) ← (M(X)) – (M) – (C) F u n c t io n : When T = 0, this instruction subtracts the value of M and the complement of C from A, and stores the results in A and C.
  • Page 91 (Ai) ← 1, or Op e r a t io n : (Mi) ← 1 F u n c t io n : This instruction sets the designated bit i of A or M. No change St a t u s fla g : Addressing mode Statement Machine codes...
  • Page 92 ARRY FLAG (C) ← 1 Op e r a t io n : F u n c t io n : This instruction sets C. St a t u s fla g : No change No change No change No change No change No change No change...
  • Page 93 ECIMAL MODE (D) ← 1 Op e r a t io n : F u n c t io n : This instruction set D. St a t u s fla g : N : No change No change No change No change No change No change...
  • Page 94 NTERRUPT DISABLE FLAG (I) ← 1 Op e r a t io n : F u n c t io n : This instruction sets I. St a t u s fla g : N : No change No change No change No change No change...
  • Page 95 RANSFER FLAG (T) ← 1 Op e r a t io n : F u n c t io n : This instruction sets T. St a t u s fla g : N : No change No change No change No change No change No change...
  • Page 96 CCUMULATOR IN MEMORY (M) ← (A) Op e r a t io n : F u n c t io n : This instruction stores the contents of A in M. The contents of A does not change. St a t u s fla g : No change Addressing mode Statement...
  • Page 97 CPU ← Stand-by state (Oscillation stopped) Op e r a t io n : F u n c t io n : This instruction resets the oscillation control F/F and the oscil- lation stops. Reset or interrupt input is needed to wake up from this mode.
  • Page 98 ORE INDEX REGISTER IN MEMORY (M) ← (X) Op e r a t io n : F u n c t io n : This instruction stores the contents of X in M. The contents of X does not change. St a t u s fla g : No change Statement...
  • Page 99 ORE INDEX REGISTER IN MEMORY (M) ← (Y) Op e r a t io n : F u n c t io n : This instruction stores the contents of Y in M. The contents of Y does not change. St a t u s fla g : No change Addressing mode...
  • Page 100 RANSFER CCUMULATOR TO INDEX REGISTER (X) ← (A) Op e r a t io n : F u n c t io n : This instruction stores the contents of A in X. The contents of A does not change. St a t u s fla g : N : N is 1 when bit 7 is 1 after the operation;...
  • Page 101 RANSFER CCUMULATOR TO INDEX REGISTER (Y) ← (A) Op e r a t io n : F u n c t io n : This instruction stores the contents of A in Y. The contents of A does not change. St a t u s fla g : N is 1 when bit 7 is 1 after the operation;...
  • Page 102 FOR NEGATIVE OR ZERO Op e r a t io n : (M) = 0 ? F u n c t io n : This instruction tests whether the contents of M are “0” or not and modifies the N and Z. St a t u s fla g : N : N is 1 when bit 7 of M is 1;...
  • Page 103 RANSFER TACK POINTER TO INDEX REGISTER (X) ← (S) Op e r a t io n : This instruction transfers the contents of S in X. F u n c t io n : St a t u s fla g : N : N is 1 when bit 7 is 1 after the operation;...
  • Page 104 RANSFER INDEX REGISTER CCUMULATOR (A) ← (X) Op e r a t io n : F u n c t io n : This instruction stores the contents of X in A. St a t u s fla g : N is 1 when bit 7 is 1 after the operation;...
  • Page 105 RANSFER INDEX REGISTER TACK POINTER (S) ← (X) Op e r a t io n : F u n c t io n : This instruction stores the contents of X in S. St a t u s fla g No change Addressing mode Statement...
  • Page 106 TY A TY A RANSFER INDEX REGISTER CCUMULATOR (A) ← (Y) Op e r a t io n : F u n c t io n : This instruction stores the contents of Y in A. St a t u s fla g : N is 1 when bit 7 is 1 after the operation;...
  • Page 107 W IT W IT CPU ← Wait state Op e r a t io n : F u n c t io n : The WIT instruction stops the internal clock but not the oscillation of the oscillation circuit is not stopped. CPU starts its function after the Timer X over flows (comes to the terminal count).

  • Page 108: Chapter 4. Notes On Use

    N OTES ON USE 4. NOTES ON USE 4.1 Notes on interrupts 4.1.1 Setting for interrupt request bit and interrupt enable bit To set an interrupt request bit and an interrupt enable bit for interrupts, execute as the following sequence: Clear an interrupt request bit to “0”...

  • Page 109: Distinction Of Interrupt Request Bit

    N OTES ON USE 4.1.3 Distinction of interrupt request bit When executing the BBC or BBS instruction to an interrupt request (request distinguish) bit of an interrupt request register (interrupt request distinguish register) immediately after this bit is set to “0” by using a data transfer instruction , execute one or more instructions before executing the BBC or BBS instruction.

  • Page 110: Notes On Programming

    N OTES ON USE 4.2 Notes on programming 4.2.1 Processor Status Register (1) Initialization of Processor Status Register Flags which affect program execution must be initialized after a reset. In particular, it is essential to initialize the T and D flags because they have an important effect on calculations. Reason After a reset, the contents of processor status register (PS) are undefined except for the I flag which is “1.”...

  • Page 111: Brk Instruction

    N OTES ON USE 4.2.2 BRK instruction (1) Method detecting interrupt source It can be detected that the BRK instruction interrupt event or the least priority interrupt event by referring the stored B flag state. Refer the stored B flag state in the interrupt routine, in this case.

  • Page 112: Jmp Instruction

    N OTES ON USE (2) Status flags in decimal mode When decimal mode is selected (D = 1), the values of three of the flags in the status register (the flags N, V, and Z) are invalid after a ADC or SBC instruction is executed. The carry flag (C) is set to “1”...

  • Page 113: Appendix 1. Instruction Cycles In Each Addressing Mode

    APPENDIX 1 Instruction Cycles in each Addressing Mode APPENDIX 1. Instruction Cycles in each Addressing Mode Clock φ controls the system timing of 740 Family. The SYNC signal and the value of PC (Program Counter) are output in every instruction fetch cycle. The Op-Code is fetched during the next half-period of φ...
  • Page 114 IM PLIED ∆ ∆ Instructions ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ Byte length Cycle number Timing φ SYNC ADDR PC +1 DATA Op -code Invalid ADDR ADDR O p - /DATA valid code...
  • Page 115 IM PLIED ∆ Instruction Byte length Cycle number Timing φ SYNC S,00 S-1,00 S-2,00 FFF4 FFF5 PC +1 ADDR (Note 1) (Note 2) (Note 1) (Note 1) (Note 2) Op - Invalid DATA code ADDR ADDR O p - code valid /DATA Notes 1 : Some p roducts are “01”...
  • Page 116 IM PLIED ∆ Instructions ∆ Byte length Timing φ SYNC ADDR PC +1 DATA Op -code Invalid ADDR ADDR O p - code valid /DATA Return from standb y state is excuted b y ex- ternal interrup t. Return from wait state is excuted b y internal or external interrup t.
  • Page 117 IM PLIED ∆ Instruction Byte length Cycle number Timing φ SYNC S+1,00 S+3,00 S,00 S+2,00 PC +1 ADDR (Note) (Note) (Note) (Note) Invalid Invalid DATA Op -code (Stack) (Stack) (Stack) 00 (Note) ADDR ADDR O p - S+2 PC S+3 PC code /DATA valid...
  • Page 118 IM PLIED ∆ Instruction Byte length Cycle number Timing φ SYNC S,00 S+2,00 S+1,00 PC +1 ADDR (Note) (Note) (Note) Invalid Invalid Invalid DATA Op -code (Stack) (Stack) ADDR 00 (Note) ADDR O p - valid code /DATA Note: Some p roducts are “01” or content of SPS flag.
  • Page 119 IM PLIED ∆ Instructions ∆ Byte length Cycle number Timing φ SYNC S,00 PC +1 ADDR (Note) Invalid Op -code DATA A or PS 00 (Note) ADDR ADDR O p - code valid /DATA Note: Some p roducts are “01” or content of SPS flag.
  • Page 120 IM PLIED ∆ Instructions ∆ Byte length Cycle number Timing φ SYNC S+1,00 PC +1 (PC+1) ADDR (Note) Invalid Op -code Invalid DATA DATA 00 (Note) ADDR ADDR O p - DATA (PC+1) valid code /DATA Note: Some p roducts are “01” or content of SPS flag.
  • Page 121 [T=0] [T=0] IM M ED IATE ∆ ∆ Instructions #$nn (T=0) ∆ ∆ #$nn (T=0) ∆ ∆ #$nn (T=0) ∆ ∆ #$nn ∆ ∆ #$nn ∆ ∆ #$nn (T=0) ∆ ∆ #$nn (T=0) ∆ ∆ #$nn ∆ ∆ #$nn ∆ ∆...
  • Page 122 AC C UM ULATOR ∆ ∆ Instructions ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ Byte length Cycle number Timing φ SYNC ADDR PC +1 Op -code Invalid DATA ADDR O p - ADDR code valid /DATA...
  • Page 123 AC C UM ULATOR BIT RELATIV E ∆ ∆ Instructions i,A,$hhll ∆ ∆ i,A,$hhll Byte length (1) With no branch Cycle number Timing φ SYNC ADDR PC +1 Invalid DATA Op -code ADDR ADDR O p - valid code valid valid /DATA...
  • Page 124 AC C UM ULATOR BIT RELATIV E ∆ ∆ Instructions i,A,$hhll ∆ ∆ i,A,$hhll Byte length (2) With branch Cycle number Timing φ SYNC (PC+2) (PC+2) ((PC+2) ± RR) PC +1 ADDR (PC+1) (PC+2) ± RR Op -code Invalid Invalid DATA Invalid ±...
  • Page 125 AC C UM ULATOR BIT ∆ ∆ Instructions ∆ ∆ Byte length Cycle number Timing φ SYNC PC +1 ADDR Invalid DATA Op -code ADDR ADDR O p - valid code /DATA...
  • Page 126 BIT RELATIV E ∆ ∆ Instructions i,$zz,$hhll ∆ ∆ i,$zz,$hhll Byte length (1) With no branch Cycle number Timing φ SYNC PC +2 PC +1 ADDR Invalid DATA Op -code DATA ADDR ADDR O p - DATA valid code valid /DATA...
  • Page 127 BIT RELATIV E ∆ ∆ Instructions i,$zz,$hhll ∆ ∆ i,$zz,$hhll Byte length (2) With branch Cycle number Timing φ SYNC (PC+3) ((PC+3) ± RR) (PC+3) PC +1 ADDR PC +2 (PC+2) (PC+3) ± RR Invalid Invalid DATA Invalid Op -code DATA ±...
  • Page 128 ZERO PAGE BIT ∆ ∆ Instructions i,$zz ∆ ∆ i,$zz Byte length Cycle number Timing φ SYNC ADDR PC +1 DATA Invalid Op -code DATA DATA ADDR ADDR O p - DATA code DA TA /DATA...
  • Page 129 ZERO PAGE [T=0] [T=0] ∆ ∆ Instructions (T=0) ∆ ∆ (T=0) ∆ ∆ ∆ ∆ (T=0) ∆ ∆ ∆ ∆ ∆ ∆ (T=0) ∆ ∆ (T=0) ∆ ∆ ∆ ∆ ∆ ∆ (T=0) ∆ ∆ (T=0) ∆ ∆ Byte length Cycle number Timing φ...
  • Page 130 ZERO PAGE ∆ ∆ Instructions ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ Byte length Cycle number Timing φ SYNC PC +1 ADDR DATA Op -code DATA Invalid DATA ADDR ADDR O p - DATA code /DATA DA TA...
  • Page 131 ZERO PAGE ∆ ∆ Instruction Byte length Cycle number Timing φ SYNC PC +1 ADDR DATA Op -code DATA Invalid DATA ADDR ADDR O p - DATA code DA TA /DATA...
  • Page 132 ZERO PAGE ∆ ∆ Instruction #$nn,$zz Byte length Cycle number Timing φ SYNC ADDR PC +1 PC +2 Op -code DATA DATA DATA ADDR ADDR O p - DATA DATA code /DATA...
  • Page 133 ZERO PAGE ∆ ∆ Instructions ∆ ∆ ∆ ∆ Byte length Cycle number Timing φ SYNC ADDR PC +1 Invalid DATA Op -code DATA ADDR ADDR O p - DATA /DATA code...
  • Page 134 Ze r o Pa g e X ∆ ∆ Instruction $zz,X (Note) Byte length Cycle number Timing φ SYNC S,SPS ADDR PC +1 +X,00 O p - DATA Invalid DATA code valid DA TA valid SPS: A selected p age b y stack p age selection b it of the C PU mode register. Note: This instruction cannot b e used for any p roducts.
  • Page 135 Ze r o Pa g e X ∆ ∆ Instruction $zz,X (Note) Byte length Cycle number Timing φ SYNC ADDR PC +1 +X+1,00 S,SPS +X,00 Low-order DA TA High-order DA TA O p - DATA Invalid valid valid code DA TA SPS: A selected p age b y stack p age selection b it of the C PU mode register.
  • Page 136 Ze r o Pa g e X ∆ ∆ Instructions $zz,X ∆ ∆ $zz,X ∆ ∆ $zz,X ∆ ∆ $zz,X ∆ ∆ $zz,X ∆ ∆ $zz,X Byte length Cycle number Timing φ SYNC (PC+1) ADDR PC +1 +X,00 DATA Invalid Invalid Op -code DATA...
  • Page 137 [T=0] ZERO PAGE X, ZERO PAGE Y ∆ ∆ Instructions $zz,X (T=0) ∆ ∆ $zz,X (T=0) ∆ ∆ $zz,X (T=0) ∆ ∆ $zz,X (T=0) ∆ ∆ $zz,X (T=0) ∆ ∆ $zz,Y ∆ ∆ $zz,X ∆ ∆ $zz,X (T=0) ∆ ∆ $zz,X (T=0) Byte length...
  • Page 138 ZERO PAGE X, ZERO PAGE Y ∆ ∆ Instructions $zz,X ∆ ∆ $zz,Y ∆ ∆ $zz,X Byte length Cycle number Timing φ SYNC (PC+1) +X(or Y ) ADDR PC +1 Op -code DATA Invalid Invalid DATA ADDR ADDR O p - DATA (or Y) /DATA...
  • Page 139 [T=0] [T=0] ABSOLUTE ∆ ∆ Instructions $hhll (T=0) ∆ ∆ $hhll (T=0) ∆ ∆ $hhll ∆ ∆ $hhll (T=0) ∆ ∆ $hhll ∆ ∆ $hhll ∆ ∆ $hhll (T=0) ∆ ∆ $hhll (T=0) ∆ ∆ $hhll ∆ ∆ $hhll ∆ ∆...
  • Page 140 ABSOLUTE ∆ ∆ Instructions $hhll ∆ ∆ $hhll ∆ ∆ $hhll ∆ ∆ $hhll ∆ ∆ $hhll ∆ ∆ $hhll Byte length Cycle number Timing φ SYNC ADDR PC +1 PC +2 Op -code DATA DATA Invalid DATA ADDR ADDR O p - DATA /DATA...
  • Page 141 ABSOLUTE ∆ ∆ Instruction $hhll Byte length Cycle number Timing φ SYNC ADDR PC +1 PC +2 DATA Op -code ADDR ADDR O p - /DATA code...
  • Page 142 ABSOLUTE ∆ ∆ Instruction $hhll Byte length Cycle number Timing φ SYNC S-1,00 ADDR S,00 (Note) PC +1 PC +2 (Note) DATA Invalid Op -code (PC +2) (PC +2) ADDR 00 (Note) ADDR O p - /DATA code Note: Some p roducts are “01” or content of SPS flag.
  • Page 143 ABSOLUTE ∆ ∆ Instructions $hhll ∆ ∆ $hhll ∆ ∆ $hhll Byte length Cycle number Timing φ SYNC ADDR PC +2 PC +1 Op -code DATA Invalid DATA ADDR ADDR O p - DATA code /DATA...
  • Page 144 [T=0] ABSOLUTE X, ABSOLUTE Y ∆ ∆ Instructions $hhll,X or Y (T=0) ∆ ∆ $hhll,X or Y (T=0) ∆ ∆ $hhll,X or Y (T=0) ∆ ∆ $hhll,X or Y (T=0) ∆ ∆ $hhll,X or Y (T=0) ∆ ∆ $hhll,Y ∆ ∆...
  • Page 145 ABSOLUTE X ∆ ∆ Instructions $hhll,X ∆ ∆ $hhll,X ∆ ∆ $hhll,X ∆ ∆ $hhll,X ∆ ∆ $hhll,X ∆ ∆ $hhll,X Byte length Cycle number Timing φ SYNC ADDR PC +2 PC +1 Op -code Invalid Invalid DATA DATA DATA ADDR ADDR O p -...
  • Page 146 ABSOLUTE X, ABSOLUTE Y ∆ ∆ Instruction $hhll,X or Y Byte length Cycle number Timing φ SYNC +X(or Y ) +X(or Y ) ADDR PC +2 PC +1 Op -code Invalid Invalid DATA DATA ADDR ADDR O p - DATA (or Y) (or Y) (or Y)
  • Page 147 IN D IREC T ∆ ∆ Instruction ($hhll) Byte length Cycle number Timing φ SYNC ADDR PC +2 PC +1 DATA Op -code ADDR ADDR O p - /DATA code BA : Basic address...
  • Page 148 ZERO PAGE IN D IREC T ∆ ∆ Instruction ($zz) Byte length Cycle number Timing φ SYNC ADDR PC +1 +1,00 Op -code DATA ADDR ADDR O p - code /DATA BA : Basic address...
  • Page 149 ZERO PAGE IN D IREC T ∆ ∆ Instruction ($zz) Byte length Cycle number Timing φ SYNC S-1,00 ADDR PC +1 S,00 (Note) (Note) DATA Invalid (PC +1) Op -code (PC +1) ADDR ADDR O p - /DATA code BA : Basic address Note: Some kind typ es are “01”...
  • Page 150 [T=0] IN D IREC T X ∆ ∆ Instructions ($zz,X) (T=0) ∆ ∆ ($zz,X) (T=0) ∆ ∆ ($zz,X) (T=0) ∆ ∆ ($zz,X) (T=0) ∆ ∆ ($zz,X) (T=0) ∆ ∆ ($zz,X) (T=0) ∆ ∆ ($zz,X) (T=0) Byte length Cycle number Timing φ...
  • Page 151 IN D IREC T X ∆ ∆ Instruction ($zz,X) Byte length Cycle number Timing φ SYNC +X+1 (PC +1) ADDR PC +1 Invalid DATA Op -code Invalid DATA ADDR ADDR O p - DATA /DATA code +X+1 BA : Basic address...
  • Page 152 [T=0] [T=0] IN D IREC T Y ∆ ∆ Instructions ($zz),Y (T=0) ∆ ∆ ($zz),Y (T=0) ∆ ∆ ($zz),Y (T=0) ∆ ∆ ($zz),Y (T=0) ∆ ∆ ($zz),Y (T=0) ∆ ∆ ($zz),Y (T=0) ∆ ∆ ($zz),Y (T=0) Byte length Cycle number Timing φ...
  • Page 153 IN D IREC T Y ∆ ∆ Instruction ($zz),Y Byte length Cycle number Timing φ SYNC ADDR PC +1 DATA Invalid Op -code Invalid DATA ADDR ADDR O p - DATA /DATA code BA : Basic address C : C arry of AD...
  • Page 154 RELATIV E ∆ ∆ Instructions $hhll ∆ ∆ $hhll ∆ ∆ $hhll ∆ ∆ $hhll ∆ ∆ $hhll ∆ ∆ $hhll ∆ ∆ $hhll ∆ ∆ $hhll Byte length (1)With no branch Cycle number Timing φ SYNC ADDR PC +1 DATA Invalid Op -code...
  • Page 155 RELATIV E ∆ ∆ Instructions $hhll ∆ ∆ $hhll ∆ ∆ $hhll ∆ ∆ $hhll ∆ ∆ $hhll ∆ ∆ $hhll ∆ ∆ $hhll ∆ ∆ $hhll Byte length (2)With branch Cycle number Timing φ SYNC (PC+2) ((PC+2) ± RR) PC +1 ADDR (PC+2) ±...
  • Page 156 RELATIV E ∆ ∆ Instruction $hhll Byte length Cycle number Timing φ SYNC (PC+2) ((PC+2) ± RR) PC +1 ADDR (PC+2 ) ± RR (PC+1) (PC+2) Invalid Op -code Invalid DATA ± RR (PC +1) ADDR (PC +2) ((PC+2) ± RR) ADDR O p - ((PC+2)
  • Page 157 SPEC IAL PAGE ∆ ∆ Instruction \$hhll Byte length Cycle number Timing φ SYNC S-1,00 PC +1 S,00 (Note) ADDR (Note) Invalid (PC +1) DATA Op -code (PC +1) ADDR 00 (Note) ADDR O p - code /DATA BA : Basic address Note : Some p roducts are “01”...
  • Page 158 [T=1] [T=1] IM M ED IATE ∆ ∆ Instructions #$nn (T=1) ∆ ∆ #$nn (T=1) ∆ ∆ #$nn (T=1) ∆ ∆ #$nn (T=1) ∆ ∆ #$nn (T=1) Byte length Cycle number Timing φ SYNC ADDR PC +1 X,00 DATA DATA DATA Invalid Op -code...
  • Page 159 [T=1] [T=1] IM M ED IATE ∆ ∆ Instruction #$nn (T=1) Byte length Cycle number Timing φ SYNC ADDR PC +1 X,00 DATA DATA DATA Op -code ADDR ADDR O p - DA TA DA TA code /DATA...
  • Page 160 [T=1] [T=1] IM M ED IATE ∆ ∆ Instruction #$nn (T=1) Byte length Cycle number Timing φ SYNC ADDR PC +1 X,00 Invalid DATA Op -code DATA DATA ADDR ADDR O p - DATA DATA /DATA code...
  • Page 161 [T=1] [T=1] ZERO PAGE ∆ ∆ Instructions (T=1) ∆ ∆ (T=1) ∆ ∆ (T=1) ∆ ∆ (T=1) ∆ ∆ (T=1) Byte length Cycle number Timing φ SYNC X,00 ADDR PC +1 DATA DA TA Invalid DATA Op -code DATA ADDR ADDR O p - DA TA...
  • Page 162 [T=1] [T=1] ZERO PAGE ∆ ∆ Instruction (T=1) Byte length Cycle number Timing φ SYNC ADDR PC +1 X,00 DATA DATA DATA Op -code ADDR ADDR O p - DA TA DA TA /DATA code...
  • Page 163 [T=1] [T=1] ZERO PAGE ∆ ∆ Instruction (T=1) Byte length Cycle number Timing φ SYNC ADDR PC +1 X,00 Invalid DATA Op -code DATA DATA ADDR ADDR O p - DATA DATA /DATA code...
  • Page 164 [T=1] [T=1] ZERO PAGE X ∆ ∆ Instructions $zz,X (T=1) ∆ ∆ $zz,X (T=1) ∆ ∆ $zz,X (T=1) ∆ ∆ $zz,X (T=1) ∆ ∆ $zz,X (T=1) Byte length Cycle number Timing φ SYNC (PC+1) ADDR PC +1 X,00 DATA DATA Invalid Invalid DATA...
  • Page 165 [T=1] [T=1] ZERO PAGE X ∆ ∆ Instruction $zz,X (T=1) Byte length Cycle number Timing φ SYNC (PC+1) ADDR PC +1 X,00 DATA DATA DATA Invalid Op -code ADDR ADDR O p - DA TA DA TA /DATA code...
  • Page 166 [T=1] [T=1] ZERO PAGE X ∆ ∆ $zz,X (T=1) Instruction Byte length Cycle number Timing φ SYNC (PC+1) ADDR PC +1 X,00 DATA Invalid Invalid Op -code DATA DATA ADDR ADDR O p - DATA DATA /DATA code...
  • Page 167 [T=1] [T=1] ABSOLUTE ∆ ∆ Instructions $hhll (T=1) ∆ ∆ $hhll (T=1) ∆ ∆ $hhll (T=1) ∆ ∆ $hhll (T=1) ∆ ∆ $hhll (T=1) Byte length Cycle number Timing φ SYNC ADDR PC +2 PC +1 X,00 DATA DATA DATA Invalid Op -code DATA...
  • Page 168 [T=1] [T=1] ABSOLUTE ∆ ∆ Instruction $hhll (T=1) Byte length Cycle number Timing φ SYNC ADDR X,00 PC +1 PC +2 DATA DATA DATA Op -code ADDR ADDR O p - DA TA DA TA code /DATA...
  • Page 169 [T=1] [T=1] ABSOLUTE ∆ ∆ Instruction $hhll (T=1) Byte length Cycle number Timing φ SYNC X,00 ADDR PC +1 PC +2 Invalid DATA DATA Op -code DATA ADDR ADDR O p - DATA DATA /DATA code...
  • Page 170 [T=1] [T=1] ABSOLUTE X, ABSOLUTE Y ∆ ∆ Instructions $hhll,X or Y (T=1) ∆ ∆ $hhll,X or Y (T=1) ∆ ∆ $hhll,X or Y (T=1) ∆ ∆ $hhll,X or Y (T=1) ∆ ∆ $hhll,X or Y (T=1) Byte length Cycle number Timing φ...
  • Page 171 [T=1] [T=1] ABSOLUTE X, ABSOLUTE Y ∆ ∆ Instruction $hhll,X or Y (T=1) Byte length Cycle number Timing φ SYNC +X(or Y ) +X(or Y ) ADDR PC +2 X,00 PC +1 DATA DATA DATA Invalid Op -code ADDR ADDR O p - DA TA DA TA...
  • Page 172 [T=1] [T=1] ABSOLUTE X, ABSOLUTE Y ∆ ∆ Instruction $hhll,X or Y (T=1) Byte length Cycle number Timing φ SYNC +X(or Y ) +X(or Y ) ADDR PC +2 X,00 PC +1 DATA Invalid Invalid Op -code DATA DATA ADDR ADDR O p - DATA...
  • Page 173 [T=1] IN D IREC T X ∆ ∆ Instructions ($zz,X) (T=1) ∆ ∆ ($zz,X) (T=1) ∆ ∆ ($zz,X) (T=1) ∆ ∆ ($zz,X) (T=1) ∆ ∆ ($zz,X) (T=1) Byte length Cycle number Timing φ SYNC (PC+1) ADDR PC +1 X,00 +1,00 Op - DATA DATA...
  • Page 174 [T=1] IN D IREC T X ∆ ∆ Instruction ($zz,X) (T=1) Byte length Cycle number Timing φ SYNC (PC+1) +X+1 ADDR PC +1 X,00 DATA DATA DATA Invalid Op -code ADDR ADDR O p - DATA DATA /DATA code BA : Basic address...
  • Page 175 [T=1] IN D IREC T X ∆ ∆ Instruction ($zz,X) (T=1) Byte length Cycle number Timing φ SYNC (PC+1) +X +1 ADDR PC +1 X,00 Op - DATA Invalid Invalid DATA DATA code ADDR ADDR O p - DATA DATA /DATA code BA : Basic address...
  • Page 176 [T=1] [T=1] IN D IREC T Y ∆ ∆ Instructions ($zz),Y (T=1) ∆ ∆ ($zz),Y (T=1) ∆ ∆ ($zz),Y (T=1) ∆ ∆ ($zz),Y (T=1) ∆ ∆ ($zz),Y (T=1) Byte length Cycle number Timing φ SYNC ADDR PC +1 X,00 DATA DATA Op -code Invalid...
  • Page 177 [T=1] [T=1] IN D IREC T Y ∆ ∆ Instruction ($zz),Y (T=1) Byte length Cycle number Timing φ SYNC ADDR PC +1 X,00 DATA DATA DATA Invalid Op -code ADDR ADDR O p - DA TA DA TA /DATA code BA : Basic address C : C arry of AD...
  • Page 178 [T=1] [T=1] IN D IREC T Y ∆ ∆ Instruction ($zz),Y (T=1) Byte length Cycle number Timing φ SYNC ADDR PC +1 X,00 Op - DATA Invalid Invalid DATA DATA code ADDR ADDR Op - DATA DATA code /DATA BA : Basic address C : C arry of AD...

  • Page 179: Appendix 2. 740 Family Machine Language Instruction Table

    APPENDIX 2 740 Family Machine Language Instruction Table APPENDIX 2. 740 Family Machine Language Instruction Table Parameter INSTRUCTION CODE FLAG CYCLE BYTE SYMBOL FUNCTION NOTE NUMBER NUMBER Classification N V T B D I Z C LDA # $ nn (A)←nn 1 0 1 0 1 0 0 1...
  • Page 180 740 Family Machine Language Instruction Table Parameter INSTRUCTION CODE FLAG BYTE CYCLE SYMBOL FUNCTION NOTE NUMBER NUMBER Classification N V T B D I Z C ADC # $ nn (A)←(A)+nn+(C) 0 1 1 0 1 0 0 1 <B2> ADC $ zz (A)←(A)+(M)+(C) where...
  • Page 181 740 Family Machine Language Instruction Table INSTRUCTION CODE FLAG Parameter SYMBOL BYTE CYCLE FUNCTION NOTE N V T B D I Z C NUMBER NUMBER Classification (A)←(A) nn AND # $ nn 0 0 1 0 1 0 0 1 <B2>...
  • Page 182 740 Family Machine Language Instruction Table INSTRUCTION CODE FLAG Parameter BYTE CYCLE SYMBOL FUNCTION NOTE NUMBER NUMBER Classification N V T B D I Z C  Left Shift C ←A ← 0 0 0 0 0 1 0 1 0 ...
  • Page 183 740 Family Machine Language Instruction Table INSTRUCTION CODE Parameter FLAG CYCLE BYTE NOTE SYMBOL FUNCTION NUMBER NUMBER Classification N V T B D I Z C (PC) ← (PC)+2+Rel 1 0 0 0 0 0 0 0 BRA $ hhII <B2>...
  • Page 184 740 Family Machine Language Instruction Table Symbol Symbol Means Means Accumulator High-order byte of address (0—255) Bit i of accumulator Low-order byte of address (0—255) Zero page address (0—255) Index register X Index register Y Date at (0—255) Memory Data at (0—7) Bit i of memory i i i Data at (0—7)

  • Page 185: Appendix 3. 740 Family List Of Instruction Codes

    APPENDIX 3 740 Family Iist of Instruction Codes APPENDIX 3. 740 Family Iist of Instruction Codes – D 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 Hexadecimal – D notation — — 0000 0, ZP IND, X...
  • Page 186 740 Family Iist of Instruction Codes MEMORANDUM...
  • Page 187 SOFTWARE MANUAL 740 Family Sep. First Edition 1997 Editioned by Committee of editing of Mitsubishi Semiconductor USER’S MANUAL Published by Mitsubishi Electric Corp., Semiconductor Marketing Division This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation.
  • Page 188 Software Manual 740 Family MITSUBISHI ELECTRIC CORPORATION HEAD OFFICE: MITSUBISHI DENKI BLDG., MARUNOUCHI, TOKYO 100. TELEX: J24532 CABLE: MELCO TOKYO New publication, effective Sep. 1997. © 1997 MITSUBISHI ELECTRIC CORPORATION. Specifications subject to change without notice.

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