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[T=1]
[T=1]
∆
Instructions
:
ADC
∆
AND
∆
EOR
∆
ORA
∆
SBC
Byte length
:
2
Cycle number
:
9
Timing
:
φ
SYNC
R/W
RD
WR
ADDR
PC
Op -code
DATA
ADDR
H
PC
H
ADDR
L
Op -
PC
L
/DATA
code
BA : Basic address
C : C arry of AD
+Y
L
170
IN D IREC T Y
∆
($zz),Y
(T=1)
∆
($zz),Y
(T=1)
∆
($zz),Y
(T=1)
∆
($zz),Y
(T=1)
∆
($zz),Y
(T=1)
B A
B A
L
PC +1
,00
,00
AD
BA
L
L
PC
H
00
PC
BA
L
L
BA
BA
A D
L
L
L
+1
+1
+1
AD
+Y
AD
+Y
L
L
L
AD
H
AD
+C
H
DATA
Invalid
AD
H
AD
AD
+C
H
H
A D
A D
DATA
L
L
A D
H
+Y
1
+Y
X,00
DATA
Invalid
2
1
00
DATA
X
X
X
2
NEW
DATA
NEW
DATA
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