∆
Instruction
:
DIV
Byte length
:
2
Cycle number
:
16
Timing
:
φ
SYNC
R/W
RD
WR
ADDR
PC
PC +1
O p -
DATA
AD
code
SPS: A selected p age b y stack p age selection b it of the C PU mode register.
Note: This instruction cannot b e used for any p roducts.
Ze r o Pa g e X
∆
$zz,X (Note)
A D
L
+X,00
Low-order DA TA
High-order DA TA
In-
L
valid
AD
+X+1,00
L
Invalid
S,SPS
In-
NEW
valid
DA TA
129