Page 1 ADVANCED AND EVER ADVANCING MITSUBISHI ELECTRIC MITSUBISHI 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY M16C/60 M16C/20 SERIES Software Manual MITSUBISHI ELECTRIC...
Page 2 Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product...
Page 3 16-bit microcomputer called the M16C/60 series and M16C/20 series, describing its CPU features and instruc- tion architecture. Please use this manual to have a good understanding of the M16C/60 series and M16C/20 se- ries software so you can take full advantage of its func- tions.
Page 4 Chapter 1 Overview _____________________________________________________ Chapter 2 ddressing Modes _______________________________________________ Chapter 3 Function ______________________________________________________ Chapter 4 Instruction Code/Number of Cycles _________________________________ Chapter 5 Interrupt ______________________________________________________...
Page 5 Using This Manual This manual is written for the M16C/60 series and M16C/20 series software. This manual can be used for all types of microcomputers having the M16C/60 series CPU core. The reader of this manual is expected to have the basic knowledge of electric and logic circuits and microcomputers.
Page 6 Software manual Detailed description about operation of each devel- instruction (assembly language) devel- opment opment System evaluation M16C Family Line-up M16C Family M16C/80 Series M16C/80 Group M16C/60 Series M16C/60 Group M16C/61 Group M16C/62 Group M16C/20 Series M16C/20 Group M16C/21 Group...
Page 7: Table Of Contents
Table of Contents Chapter 1 Overview ___________________________________________________ Features of M16C/60 series and M16C/20 series ..............2 Address Space ........................3 Register Configuration ......................4 Flag Register(FLG) .........................6 Register Bank .........................8 Internal State after Reset is Cleared ..................9 Data Types ........................... 10 Data Arrangement ........................ 15 Instruction Format .........................17...
Page 8 Quick Reference in Alphabetic Order See page for See page for See page for See page for Mnemonic Mnemonic instruction code function function instruction code /number of cycles /number of cycles DIVU DIVX ADCF DSBB DSUB ADJNZ ENTER EXITD BAND EXTS BCLR FCLR...
Page 9 Quick Reference in Alphabetic Order See page for See page for See page for See page for Mnemonic Mnemonic function instruction code instruction code function /number of cycles /number of cycles MOV Dir MOVHH MOVHL MOVLH SBJNZ MOVLL MULU SMOVB SMOVF SSTR STCTX...
Page 10 Quick Reference by Function See page for See page for Mnemonic Function Content instruction code function /number of cycles Transfer Transfer MOVA Transfer effective address MOVDir Transfer 4-bit data Restore register/memory POPM Restore multiple registers PUSH Save register/memory/immediate data PUSHA Save effective address PUSHM Save multiple registers...
Page 11 Quick Reference by Function Content See page for See page for Function Mnemonic instruction code function /number of cycles Arithmetic DADD Decimal add without carry Decrement Signed divide DIVU Unsigned divide DIVX Singed divide DSBB Decimal subtract with borrow DSUB Decimal subtract without borrow EXTS Extend sign...
Page 12 Quick Reference by Function Content See page for See page for Function Mnemonic instruction code function /number of cycles Other LDCTX Restore context LDINTB Transfer to INTB register LDIPL Set interrupt enable level No operation POPC Restore control register PUSHC Save control register REIT Return from interrupt...
Page 13 Quick Reference by Addressing (general instruction addressing) Addressing See page See page for Mnemonic for function instruction code /number of cycles ADCF ADJNZ DADC DADD DIVU DIVX DSBB DSUB ENTER EXTS JMPI JMPS JSRI JSRS 1 Has special instruction addressing. *2 Only R1L can be selected.
Page 14 Quick Reference by Addressing (general instruction addressing) Addressing See page See page for Mnemonic for function instruction code /number of cycles LDINTB LDIPL MOVA MOV Dir MULU POPM PUSH PUSHA PUSHM ROLC RORC SBJNZ STCTX *1 Has special instruction addressing. Quick Reference-7...
Page 15 Quick Reference by Addressing (general instruction addressing) Addressing See page See page for Mnemonic for function instruction code /number of cycles STNZ STZX XCHG Quick Reference-8...
Page 16 Quick Reference by Addressing (special instruction addressing) See page for See page Addressing Mnemonic instruction for function code /number of cycles ADJNZ JCnd JMPI JSRI LDCTX POPC POPM PUSHC PUSHM SBJNZ STCTX *1 Has general instruction addressing. *2 INTBL and INTBH cannot be set simultaneously when using the LDINTB instruction. Quick Reference-9...
Page 17 Quick Reference by Addressing (bit instruction addressing) Addressing See page See page for Mnemonic for function instruction code /number of cycles BAND BCLR BM Cnd BNAND BNOR BNOT BNTST BNXOR BSET BTST BTSTC BTSTS BXOR FCLR FSET Quick Reference-10...
Page 18: Chapter 1 Overview
Chapter 1 Overview 1.1 Features of M16C/60 series and M16C/20 series 1.2 Address Space 1.3 Register Configuration 1.4 Flag Register (FLG) 1.5 Register Bank 1.6 Internal State after Reset is Cleared 1.7 Data Types 1.8 Data Arrangement 1.9 Instruction Format...
Page 19: Features Of M16C/60 Series And M16C/20 Series
The M16C/60 series and M16C/20 series are single-chip microcomputer developed for built-in applications where the microcomputer is built into applications equipment. The M16C/60 series and M16C/20 series support instructions suitable for the C language with frequently used instructions arranged in one- byte op-code. Therefore, it allows you for efficient program development with few memory capacity regardless of whether you are using the assembly language or C language.
Page 20: Address Space
M16C/60 series and M16C/20 series, the SFR area extends from 003FF toward lower addresses. Addresses from 00400 on make up a memory area. In individual models of the M16C/60 series and M16C/20 series, a RAM area extends from address 00400 toward higher addresses, and a ROM area extends from FFFFF toward lower addresses.
Page 21: Register Configuration
Chapter 1 Overview 1.3 Register Configuration 1.3 Register Configuration The central processing unit (CPU) contains the 13 registers shown in Figure 1.3.1. Of these registers, R0, R1, R2, R3, A0, A1, and FB each consist of two sets of registers configuring two register banks. b8b7 ...
Page 22 Chapter 1 Overview 1.3 Register Configuration (2) Address registers (A0 and A1) The address registers (A0 and A1) consist of 16 bits, and have the similar functions as the data regis- ters. These registers are used for address register-based indirect addressing and address register- based relative addressing.
Page 23: Flag Register(Flg)
Chapter 1 Overview 1.4 Flag Register (FLG) 1.4 Flag Register (FLG) Figure 1.4.1 shows a configuration of the flag register (FLG). The function of each flag is detailed below. (1) Bit 0: Carry flag (C flag) This flag holds a carry, borrow, or shifted-out bit that has occurred in the arithmetic/logic unit. (2) Bit 1: Debug flag (D flag) This flag enables a single-step interrupt.
Page 24 Chapter 1 Overview 1.4 Flag Register (FLG) (10) Bits 12-14: Processor interrupt priority level (IPL) The processor interrupt priority level (IPL) consists of three bits, allowing you to specify eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt’s priority level is higher than the processor interrupt priority level (IPL), this interrupt is enabled.
Page 25: Register Bank
Chapter 1 Overview 1.5 Register Bank 1.5 Register Bank The M16C has two register banks, each configured with data registers (R0, R1, R2, and R3), address registers (A0 and A1), and frame base register (FB). These two register banks are switched over by the register bank select flag (B flag) of the flag register (FLG).
Page 26: Internal State After Reset Is Cleared
Chapter 1 Overview 1.6 Internal State after Reset is Cleared 1.6 Internal State after Reset is Cleared The following lists the content of each register after a reset is cleared. • Data registers (R0, R1, R2, and R3): 0000 • Address registers (A0 and A1): 0000 •...
Page 27: Data Types
Chapter 1 Overview 1.7 Data Types 1.7 Data Types There are four data types: integer, decimal, bit, and string. 1.7.1 Integer An integer can be a signed or an unsigned integer. A negative value of a signed integer is represented by two’s complement.
Page 28 Chapter 1 Overview 1.7 Data Types 1.7.2 Decimal This type of data can be used in DADC, DADD, DSBB, and DSUB. Pack format (2 digits) Pack format (4 digits) Figure 1.7.2 Decimal data...
Page 29 Chapter 1 Overview 1.7 Data Types 1.7.3 Bits (1) Register bits Figure 1.7.3 shows register bit specification. Register bits can be specified by register direct (bit, Rn or bit, An). Use bit, Rn to specify a bit in data register (Rn); use bit, An to specify a bit in address register (An). Bits in each register are assigned bit numbers 0-15, from LSB to MSB.
Page 30 Chapter 1 Overview 1.7 Data Types (1) Bit specification by bit, base Figure 1.7.5 shows the relationship between memory map and bit map. Memory bits can be handled as an array of consecutive bits. Bits can be specified by a given combina- tion of bit and base.
Page 31 Chapter 1 Overview 1.7 Data Types (2) SB/FB relative bit specification For SB/FB-based relative addressing, use bit 0 of the address that is the sum of the address set to static base register (SB) or frame base register (FB) plus the address set to base as the reference (= 0), and set your desired bit position to bit.
Page 32 Chapter 1 Overview 1.7 Data Types 1.7.4 String String is a type of data that consists of a given length of consecutive byte (8-bit) or word (16-bit) data. This data type can be used in three types of string instructions: character string backward transfer (SMOVB instruction), character string forward transfer (SMOVF instruction), and specified area initialize (SSTR instruction).
Page 33: Data Arrangement
Chapter 1 Overview 1.8 Data Arrangement 1.8 Data Arrangement 1.8.1 Data Arrangement in Register Figure 1.8.1 shows the relationship between a register’s data size and bit numbers. Nibble (4-bit) data Byte (8-bit) data Word (16-bit) data Long word (32-bit) data Figure 1.8.1 Data arrangement in register...
Page 34 Chapter 1 Overview 1.8 Data Arrangement 1.8.2 Data Arrangement in Memory Figure 1.8.2 shows data arrangement in memory. Figure 1.8.3 shows some examples of operation. DATA DATA(L) DATA(H) Byte (8-bit) data Word (16-bit) data DATA(L) DATA(LL) DATA(M) DATA(LH) DATA(H) DATA(HL) DATA(HH) Long Word (32-bit) data 20-bit (Address) data...
Page 35: Instruction Format
Chapter 1 Overview 1.9 Instruction Format 1.9 Instruction Format The instruction format can be classified into four types: generic, quick, short, and zero. The number of instruction bytes that can be chosen by a given format is least for the zero format, and increases succes- sively for the short, quick, and generic formats in that order.
Page 36: Vector Table
Chapter 1 Overview 1.10 Vector Table 1.10 Vector Table The vector table comes in two types: a special page vector table and an interrupt vector table. The special page vector table is a fixed vector table. The interrupt vector table can be a fixed or a variable vector table. 1.10.1 Fixed Vector Table The fixed vector table is an address-fixed vector table.
Page 37 Chapter 1 Overview 1.10 Vector Table 1.10.2 Variable Vector Table The variable vector table is an address-variable vector table. Specifically, this vector table is a 256-byte interrupt vector table that uses the value indicated by the interrupt table register (INTB) as the entry address (IntBase).
Page 38 Chapter 2 Addressing Modes 2.1 Addressing Modes 2.2 Guide to This Chapter 2.3 General Instruction Addressing 2.4 Special Instruction Addressing 2.5 Bit Instruction Addressing...
Page 39: Chapter 2 Addressing Modes
2.1 Addressing Modes 2.1 Addressing Modes This section describes addressing mode-representing symbols and operations for each addressing mode. The M16C/60 series and M16C/20 series have three addressing modes outlined below. (1) General instruction addressing This addressing accesses an area from address 00000...
Page 40: Guide To This Chapter
Chapter 2 Addressing Modes 2.2 Guide to This Chapter 2.2 Guide to This Chapter The following shows how to read this chapter using an actual example. Address register relative The value indicated by displacement dsp:8[A0] (dsp) plus the content of address dsp:8[A1] register (A0/A1)—added not includ- Register...
Page 41: General Instruction Addressing
Chapter 2 Addressing Modes 2.3 General Instruction Addressing 2.3 General Instruction Addressing Immediate #IMM8 The immediate data indicated by #IMM #IMM is the object to be operated on. #IMM8 #IMM16 #IMM16 #IMM20 #IMM20 Register direct Register The specified register is the object to be operated on.
Page 42 Chapter 2 Addressing Modes 2.3 General Instruction Addressing Address register relative The value indicated by displacement dsp:8[A0] Memory (dsp) plus the content of address dsp:8[A1] register (A0/A1)—added not including dsp:16[A0] the sign bits—constitutes the effective Register address to be operated on. dsp:16[A1] A0 / A1 address...
Page 43 Chapter 2 Addressing Modes 2.3 General Instruction Addressing Stack pointer relative dsp:8[SP] The address indicated by the content of stack Memory pointer (SP) plus the value indicated by If the dsp value is negative displacement (dsp)—added including the sign bits—constitutes the effective address to be operated on.
Page 44: Specific Instruction Addressing
Chapter 2 Addressing Modes 2.4 Special Instruction Addressing 2.4 Special Instruction Addressing 20-bit absolute The value indicated by abs20 constitutes abs20 Memory the effective address to be operated on. The effective address range is 00000 FFFFF abs20 This addressing can be used in LDE, STE, JSR, and JMP instructions.
Page 45 Chapter 2 Addressing Modes 2.4 Special Instruction Addressing 32-bit register direct SHL, SHA instructions The 32-bit concatenated register content of two R2R0 specified registers is the object to be operated R2R0 R3R1 R3R1 A1A0 This addressing can be used in SHL, SHA, JMPI, and JSRI instructions.
Page 46 Chapter 2 Addressing Modes 2.4 Special Instruction Addressing Program counter relative • If the jump length specifier (.length) label is (.S)... Memory the base address plus the value indicated by displacement (dsp)— Base address added not including the sign bits— constitutes the effective address.
Page 47: Bit Instruction Addressing
Chapter 2 Addressing Modes 2.5 Bit Instruction Addressing 2.5 Bit Instruction Addressing This addressing can be used in the following instructions: BCLR, BSET, BNOT, BTST, BNTST, BAND, BNAND, BOR, BNOR, BXOR, BNXOR, BM Cnd , BTSTS, BTSTC Register direct The specified register bit is the object bit,R0 bit , R0 to be operated on.
Page 48 Chapter 2 Addressing Modes 2.5 Bit Instruction Addressing Address register relative base:8[A0] The bit that is as much away from bit 0 at the address indi- base:8[A1] cated by base as the number of base:16[A0] bits indicated by address register (A0/A1) is the object to be base:16[A1] operated on.
Page 49 Chapter 2 Addressing Modes 2.5 Bit Instruction Addressing FB relative The bit that is as much away from bit 0 at bit,base:8[FB] Memory the address indicated by frame base register (FB) plus the value indicated by base (added including the sign bit) as the If the base value is negative number of bits indicated by bit is the object to be operated on.
Page 50: Chapter 3 Functions
Chapter 3 Functions 3.1 Guide to This Chapter 3.2 Functions...
Page 51: Guide To This Chapter
Chapter 3 Functions 3.1 Guide to This Chapter 3.1 Guide to This Chapter This chapter describes the functionality of each instruction by showing syntax, operation, function, select- able src/dest, flag changes, description examples, and related instructions. The following shows how to read this chapter by using an actual page as an example. Chapter 3 Functions 3.2 Functions Transfer...
Page 52 Chapter 3 Functions 3.1 Guide to This Chapter (1) Mnemonic Indicates the mnemonic explained in this page. (2) Instruction code/Number of Cycles Indicates the page in which instruction code/number of cycles is listed. Refer to this page for instruction code and number of cycles. (3) Syntax Indicates the syntax of the instruction using symbols.
Page 53 Chapter 3 Functions 3.1 Guide to This Chapter Chapter 3 Functions 3.2 Functions Transfer MOVe [ Instruction Code/Number of Cycles ] [ Syntax ] Page=195 MOV.size (:format) src,dest G , Q , Z , S (Can be specified) B , W [ Operation ] dest [ Function ]...
Page 54 Chapter 3 Functions 3.1 Guide to This Chapter (4) Operation Explains the operation of the instruction using symbols. (5) Function Explains the function of the instruction and precautions to be taken when using the instruction. (6) Selectable src / dest (label) If the instruction has an operand, this indicates the format you can choose for the operand.
Page 55 Chapter 3 Functions 3.1 Guide to This Chapter The following explains the syntax of each jump instruction—JMP, JPMI, JSR, and JSRI by using an actual example. Chapter 3 Functions 3.2 Functions Unconditional jump JuMP [ Instruction Code/Number of Cycles ] [ Syntax ] Page=195 JMP (.length) label...
Page 56: Functions
Chapter 3 Functions Functions Absolute value ABSolute [ Syntax ] [ Instruction Code/Number of Cycles ] ABS.size dest Page= B , W [ Operation ] dest dest [ Function ] • This instruction takes on an absolute value of dest and stores it in dest . [ Selectable dest ] dest R0L/R0...
Page 57 Chapter 3 Functions Functions Add with carry ADdition with Carry [ Syntax ] [ Instruction Code/Number of Cycles ] ADC.size src,dest Page= B , W [ Operation ] dest dest [ Function ] • This instruction adds dest , src , and C flag together and stores the result in dest . •...
Page 58 Chapter 3 Functions Functions Add carry flag ADCF ADCF ADdition Carry Flag [ Syntax ] [ Instruction Code/Number of Cycles ] ADCF.size dest Page= B , W [ Operation ] dest dest [ Function ] This instruction adds dest and C flag together and stores the result in dest . [ Selectable dest ] dest R0L/R0...
Page 59 Chapter 3 Functions Functions Add without carry ADDition [ Syntax ] [ Instruction Code/Number of Cycles ] ADD.size (:format) src,dest Page= G , Q , S (Can be specified) B , W [ Operation ] dest dest [ Function ] •...
Page 60 Chapter 3 Functions Functions [src/dest Classified by Format] G format dest R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:20[A0] dsp:20[A1] abs20 #IMM...
Page 61 Chapter 3 Functions Functions Add & conditional jump ADJNZ ADJNZ ADdition then Jump on Not Zero [ Syntax ] [ Instruction Code/Number of Cycles ] ADJNZ.size src,dest,label Page= B , W [ Operation ] dest dest if dest 0 then jump label [ Function ] •...
Page 62 Chapter 3 Functions Functions Logically AND [ Syntax ] [ Instruction Code/Number of Cycles ] Page= 149 AND.size (:format) src,dest G , S (Can be specified) B , W [ Operation ] dest dest [ Function ] • This instruction logically ANDs dest and src together and stores the result in dest . •...
Page 63 Chapter 3 Functions Functions [src/dest Classified by Format] G format dest R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:20[A0] dsp:20[A1] abs20 #IMM...
Page 64 Chapter 3 Functions Functions Logically AND bits BAND BAND Bit AND carry flag [ Syntax ] [ Instruction Code/Number of Cycles ] BAND src Page= 152 [ Operation ] [ Function ] • This instruction logically ANDs the C flag and src together and stores the result in the C flag. [ Selectable src ] bit,R0 bit,R1...
Page 65 Chapter 3 Functions Functions Clear bit BCLR BCLR Bit CLeaR [ Syntax ] [ Instruction Code/Number of Cycles ] BCLR (:format) dest Page= 152 G , S (Can be specified) [ Operation ] dest [ Function ] • This instruction stores 0 in dest . [ Selectable dest ] dest bit,R0...
Page 66 Chapter 3 Functions Functions Conditional bit transfer BM Cnd BM Cnd Bit Move Condition [ Syntax ] [ Instruction Code/Number of Cycles ] BM Cnd Page= 154 dest [ Operation ] if true then dest else dest [ Function ] •...
Page 67 Chapter 3 Functions Functions Logically AND inverted bits BNAND BNAND Bit Not AND carry flag [ Syntax ] [ Instruction Code/Number of Cycles ] Page= 155 BNAND [ Operation ] ______ [ Function ] • This instruction logically ANDs the C flag and inverted src together and stores the result in the C flag. [ Selectable src ] bit,R0 bit,R1...
Page 68 Chapter 3 Functions 3.2 Functions Logically OR inverted bits BNOR BNOR Bit Not OR carry flag [ Syntax ] [ Instruction Code/Number of Cycles ] BNOR src Page= [ Operation ] ______ [ Function ] • This instruction logically ORs the C flag and inverted src together and stores the result in the C flag. [ Selectable src ] bit,R0 bit,R1...
Page 69 Chapter 3 Functions 3.2 Functions Invert bit BNOT BNOT Bit NOT [ Syntax ] [ Instruction Code/Number of Cycles ] BNOT(:format) dest Page= 156 G , S (Can be specified) [ Operation ] ________ dest dest [ Function ] • This instruction inverts dest and stores the result in dest . [ Selectable dest ] dest bit,R0...
Page 70 Chapter 3 Functions 3.2 Functions Test inverted bit BNTST BNTST Bit Not TeST [ Syntax ] [ Instruction Code/Number of Cycles ] BNTST Page= 157 [ Operation ] ______ [ Function ] • This instruction transfers inverted src to the Z flag and inverted src to the C flag. [ Selectable src ] bit,R0 bit,R1...
Page 71 Chapter 3 Functions 3.2 Functions Exclusive OR inverted bits BNXOR BNXOR Bit Not eXclusive OR carry flag [ Syntax ] [ Instruction Code/Number of Cycles ] Page= 158 BNXOR [ Operation ] ______ [ Function ] • This instruction exclusive ORs the C flag and inverted src and stores the result in the C flag. [ Selectable src ] bit,R0 bit,R1...
Page 72 Chapter 3 Functions 3.2 Functions Logically OR bits Bit OR carry flag [ Syntax ] [ Instruction Code/Number of Cycles ] Page= 158 [ Operation ] [ Function ] • This instruction logically ORs the C flag and src together and stores the result in the C flag. [ Selectable src ] bit,R0 bit,R1...
Page 73 Chapter 3 Functions 3.2 Functions Debug interrupt BReaK [ Syntax ] [ Instruction Code/Number of Cycles ] Page= 159 [ Operation ] – M(SP) , FLG – M(SP) M(FFFE4 [ Function ] • This instruction generates a BRK interrupt. • The BRK interrupt is a nonmaskable interrupt. [ Flag Change ] Flag *1 The flags are saved to the stack area before the BRK in-...
Page 74 Chapter 3 Functions 3.2 Functions Set bit BSET BSET Bit SET [ Syntax ] [ Instruction Code/Number of Cycles ] BSET (:format) dest Page= G , S (Can be specified) [ Operation ] dest [ Function ] • This instruction stores 1 in dest . [ Selectable dest ] dest bit,R0...
Page 75 Chapter 3 Functions 3.2 Functions Test bit BTST BTST Bit TeST [ Syntax ] [ Instruction Code/Number of Cycles ] BTST (:format) Page= 160 G , S (Can be specified) [ Operation ] ______ [ Function ] • This instruction transfers inverted src to the Z flag and non-inverted src to the C flag. [ Selectable src ] bit,R0 bit,R1...
Page 76 Chapter 3 Functions 3.2 Functions Test bit & clear BTSTC BTSTC Bit TeST & Clear [ Syntax ] [ Instruction Code/Number of Cycles ] Page= 161 BTSTC dest [ Operation ] ________ dest dest dest [ Function ] • This instruction transfers inverted dest to the Z flag and non-inverted dest to the C flag. Then it stores 0 in dest .
Page 77 Chapter 3 Functions 3.2 Functions Test bit & set BTSTS BTSTS Bit TeST & Set [ Syntax ] [ Instruction Code/Number of Cycles ] Page= 162 BTSTS dest [ Operation ] ________ dest dest dest [ Function ] • This instruction transfers inverted dest to the Z flag and non-inverted dest to the C flag. Then it stores 1 in dest .
Page 78 Chapter 3 Functions 3.2 Functions Exclusive OR bits BXOR BXOR Bit eXclusive OR carry flag [ Syntax ] [ Instruction Code/Number of Cycles ] BXOR src Page= 162 [ Operation ] [ Function ] • This instruction exclusive ORs the C flag and src together and stores the result in the C flag. [ Selectable src ] bit,R0 bit,R1...
Page 79 Chapter 3 Functions 3.2 Functions Compare CoMPare [ Syntax ] [ Instruction Code/Number of Cycles ] CMP.size (:format) src,dest Page= G , Q , S (Can be specified) B , W [ Operation ] dest – [ Function ] • Each flag bit of the flag register varies depending on the result of subtraction of src from dest . •...
Page 80 Chapter 3 Functions 3.2 Functions [src/dest Classified by Format] G format dest R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:20[A0] dsp:20[A1] abs20...
Page 81 Chapter 3 Functions 3.2 Functions Decimal add with carry DADC DADC Decimal ADdition with Carry [ Instruction Code/Number of Cycles ] [ Syntax ] Page= 167 DADC.size src,dest B , W [ Operation ] dest dest [ Function ] • This instruction adds dest , src , and C flag together in decimal and stores the result in dest . [ Selectable src/dest ] dest R0L/R0...
Page 82 Chapter 3 Functions 3.2 Functions Decimal add without carry DADD DADD Decimal ADDition [ Syntax ] [ Instruction Code/Number of Cycles ] DADD.size src,dest Page= 169 B , W [ Operation ] dest dest [ Function ] • This instruction adds dest and src together in decimal and stores the result in dest . [ Selectable src/dest ] dest R0L/R0...
Page 83 Chapter 3 Functions 3.2 Functions Decrement DECrement [ Syntax ] [ Instruction Code/Number of Cycles ] Page= 171 DEC.size dest B , W [ Operation ] dest dest – [ Function ] • This instruction decrements 1 from dest and stores the result in dest . [ Selectable dest ] dest dsp:8[SB]...
Page 84 Chapter 3 Functions 3.2 Functions Signed divide DIVide [ Syntax ] [ Instruction Code/Number of Cycles ] DIV.size Page= 172 B , W [ Operation ] If the size specifier (.size) is (.B) R0L (quotient), R0H (remainder) If the size specifier (.size) is (.W) R0 (quotient), R2 (remainder) R2R0 [ Function ]...
Page 85 Chapter 3 Functions 3.2 Functions Unsigned divide DIVU DIVU DIVide Unsigned [ Syntax ] [ Instruction Code/Number of Cycles ] DIVU.size Page= 173 B , W [ Operation ] If the size specifier (.size) is (.B) R0L (quotient), R0H (remainder) If the size specifier (.size) is (.W) R0 (quotient), R2 (remainder) R2R0...
Page 86 Chapter 3 Functions 3.2 Functions Singed divide DIVX DIVX DIVide eXtension [ Syntax ] [ Instruction Code/Number of Cycles ] DIVX.size Page= 174 B , W [ Operation ] If the size specifier (.size) is (.B) R0L (quotient), R0H (remainder) If the size specifier (.size) is (.W) R0 (quotient), R2 (remainder) R2R0...
Page 87 Chapter 3 Functions 3.2 Functions Decimal subtract with borrow DSBB DSBB Decimal SuBtract with Borrow [ Syntax ] [ Instruction Code/Number of Cycles ] DSBB.size src,dest Page= 175 B , W [ Operation ] ____ dest dest – – [ Function ] •...
Page 88 Chapter 3 Functions 3.2 Functions Decimal subtract without borrow DSUB DSUB Decimal SUBtract [ Instruction Code/Number of Cycles ] [ Syntax ] Page= 177 DSUB.size src,dest B , W [ Operation ] dest dest – [ Function ] • This instruction subtracts src from dest in decimal and stores the result in dest . [ Selectable src/dest ] dest R0L/R0...
Page 89 Chapter 3 Functions 3.2 Functions Build stack frame ENTER ENTER ENTER function [ Syntax ] [ Instruction Code/Number of Cycles ] ENTER Page= [ Operation ] – M(SP) – [ Function ] • This instruction generates a stack frame. src represents the size of the stack frame. •...
Page 90 Chapter 3 Functions 3.2 Functions Deallocate stack frame EXITD EXITD EXIT and Deallocate stack frame [ Instruction Code/Number of Cycles ] [ Syntax ] Page= 180 EXITD [ Operation ] M(SP) M(SP) M(SP) [ Function ] • This instruction deallocates the stack frame and exits from the subroutine. •...
Page 91 Chapter 3 Functions 3.2 Functions Extend sign EXTS EXTS EXTend Sign [ Instruction Code/Number of Cycles ] [ Syntax ] Page= 180 EXTS.size dest B , W [ Operation ] dest EXT(dest) [ Function ] • This instruction sign extends dest and stores the result in dest . •...
Page 92 Chapter 3 Functions 3.2 Functions Clear flag register bit FCLR FCLR Flag register CLeaR [ Syntax ] [ Instruction Code/Number of Cycles ] FCLR dest Page= 181 [ Operation ] dest [ Function ] • This instruction stores 0 in dest . [ Selectable dest ] dest [ Flag Change ]...
Page 93 Chapter 3 Functions 3.2 Functions Set flag register bit FSET FSET Flag register SET [ Syntax ] [ Instruction Code/Number of Cycles ] FSET dest Page= 182 [ Operation ] dest [ Function ] • This instruction stores 1 in dest . [ Selectable dest ] dest [ Flag Change ]...
Page 94 Chapter 3 Functions 3.2 Functions Increment INCrement [ Syntax ] [ Instruction Code/Number of Cycles ] INC.size dest Page= 182 B , W [ Operation ] dest dest [ Function ] • This instruction adds 1 to dest and stores the result in dest . [ Selectable dest ] dest dsp:8[SB]...
Page 95 Chapter 3 Functions 3.2 Functions Interrupt by INT instruction INTerrupt [ Syntax ] [ Instruction Code/Number of Cycles ] Page= 183 [ Operation ] SP – M(SP) , FLG – M(SP) M(IntBase [ Function ] • This instruction generates a software interrupt specified by src . src represents a software interrupt number.
Page 96 Chapter 3 Functions 3.2 Functions Interrupt on overflow INTO INTO INTerrupt on Overflow [ Syntax ] [ Instruction Code/Number of Cycles ] INTO Page= 184 [ Operation ] SP – M(SP) , FLG – M(SP) M(FFFE0 [ Function ] • If the O flag is 1, this instruction generates an overflow interrupt. If the flag is 0, the next instruction is executed.
Page 97 Chapter 3 Functions 3.2 Functions Jump on condition J Cnd J Cnd Jump on Condition [ Syntax ] [ Instruction Code/Number of Cycles ] J Cnd label Page= 184 [ Operation ] if true then jump label [ Function ] •...
Page 98 Chapter 3 Functions 3.2 Functions Unconditional jump JuMP [ Syntax ] [ Instruction Code/Number of Cycles ] Page= 185 JMP(.length) label S , B , W , A (Can be specified) [ Operation ] label [ Function ] • This instruction causes control to jump to label. [ Selectable label ] .length label...
Page 99 Chapter 3 Functions 3.2 Functions Jump indirect JMPI JMPI JuMP Indirect [ Syntax ] [ Instruction Code/Number of Cycles ] JMPI.length Page= 187 W , A [ Operation ] When jump distance specifier (.length) is (.W) When jump distance specifier (.length) is (.A) [ Function ] •...
Page 100 Chapter 3 Functions 3.2 Functions Jump to special page JMPS JMPS JuMP Special page [ Instruction Code/Number of Cycles ] [ Syntax ] Page= 188 JMPS src [ Operation ] M( FFFFE – src [ Function ] • This instruction causes control to jump to the address set in each table of the special page vector table plus F0000 .
Page 101 Chapter 3 Functions 3.2 Functions Subroutine call Jump SubRoutine [ Instruction Code/Number of Cycles ] [ Syntax ] Page= 189 JSR(.length) label W , A (Can be specified) [ Operation ] – M(SP) – M(SP) label n denotes the number of instruction bytes. [ Function ] •...
Page 102 Chapter 3 Functions 3.2 Functions Indirect subroutine call JSRI JSRI Jump SubRoutine Indirect [ Syntax ] [ Instruction Code/Number of Cycles ] JSRI.length src Page= W , A [ Operation ] When jump distance specifier (.length) is (.W) When jump distance specifier (.length) is (.A) –...
Page 103 Chapter 3 Functions 3.2 Functions Special page subroutine call JSRS JSRS Jump SubRoutine Special page [ Syntax ] [ Instruction Code/Number of Cycles ] JSRS src Page= 191 [ Operation ] – M(SP) – M(SP) M ( FFFFE – src [ Function ] •...
Page 104 Chapter 3 Functions 3.2 Functions Transfer to control register LoaD Control register [ Syntax ] [ Instruction Code/Number of Cycles ] src,dest Page= 191 [ Operation ] dest [ Function ] • This instruction transfers src to the control register indicated by dest . If src is memory, the required memory capacity is 2 bytes.
Page 105 Chapter 3 Functions 3.2 Functions Restore context LDCTX LDCTX LoaD ConTeXt [ Syntax ] [ Instruction Code/Number of Cycles ] LDCTX abs16,abs20 Page= 192 [ Function ] • This instruction restores task context from the stack area. • Set the RAM address that contains the task number in abs16 and the start address of table data in abs20. •...
Page 106 Chapter 3 Functions 3.2 Functions Transfer from extended data area LoaD from EXtra far data area [ Syntax ] [ Instruction Code/Number of Cycles ] LDE.size src,dest Page= 193 B , W [ Operation ] dest [ Function ] • This instruction transfers src from extended area to dest . •...
Page 107 Chapter 3 Functions 3.2 Functions Transfer to INTB register LDINTB LDINTB LoaD INTB register [ Syntax ] [ Instruction Code/Number of Cycles ] LDINTB Page= 194 [ Operation ] INTBHL [ Function ] • This instruction transfers src to INTB. •...
Page 108 Chapter 3 Functions 3.2 Functions Set interrupt enable level LDIPL LDIPL LoaD Interrupt Permission Level [ Syntax ] [ Instruction Code/Number of Cycles ] LDIPL src Page= 195 [ Operation ] [ Function ] • This instruction transfers src to IPL. [ Selectable src ] #IMM *1 The range of values that can be taken on is 0 <...
Page 109 Chapter 3 Functions 3.2 Functions Transfer MOVe [ Syntax ] [ Instruction Code/Number of Cycles ] MOV.size (:format) src,dest Page= 195 (Can be specified) G , Q , Z , S B , W [ Operation ] dest [ Function ] •...
Page 110 Chapter 3 Functions 3.2 Functions [src/dest Classified by Format] G format dest R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:20[A0] dsp:20[A1] abs20...
Page 111 Chapter 3 Functions 3.2 Functions Transfer effective address MOVA MOVA MOVe effective Address [ Syntax ] [ Instruction Code/Number of Cycles ] MOVA src,dest Page= 202 [ Operation ] dest EVA(src) [ Function ] • This instruction transfers the affective address of src to dest . [ Selectable src/dest ] dest R0L/R0...
Page 112 Chapter 3 Functions 3.2 Functions Transfer 4-bit data MOV Dir MOV Dir MOVe nibble [ Syntax ] [ Instruction Code/Number of Cycles ] MOV Dir src,dest Page= 203 [ Operation ] Operation H4:dest H4:src L4:dest H4:src H4:dest L4:src L4:dest L4:src [ Function ] •...
Page 113 Chapter 3 Functions 3.2 Functions Signed multiply MULtiple [ Syntax ] [ Instruction Code/Number of Cycles ] MUL.size src,dest Page= 205 B , W [ Operation ] dest dest [ Function ] • This instruction multiplies src and dest together including the sign bits and stores the result in dest . •...
Page 114 Chapter 3 Functions 3.2 Functions Unsigned multiply MULU MULU MULtiple Unsigned [ Syntax ] [ Instruction Code/Number of Cycles ] Page= 207 MULU.size src,dest B , W [ Operation ] dest dest [ Function ] • This instruction multiplies src and dest together not including the sign bits and stores the result in dest . •...
Page 115 Chapter 3 Functions 3.2 Functions Two’s complement NEGate [ Syntax ] [ Instruction Code/Number of Cycles ] NEG.size dest Page= 209 B , W [ Operation ] dest – dest [ Function ] • This instruction takes the 2’s complement of dest and stores the result in dest . [ Selectable dest ] dest R0L/R0...
Page 116 Chapter 3 Functions 3.2 Functions No operation No OPeration [ Instruction Code/Number of Cycles ] [ Syntax ] Page= 209 [ Operation ] [ Function ] • This instruction adds 1 to PC. [ Flag Change ] Flag Change [ Description Example ]...
Page 117 Chapter 3 Functions 3.2 Functions Invert all bits [ Syntax ] [ Instruction Code/Number of Cycles ] NOT.size (:format) dest Page= 210 (Can be specified) G , S B , W [ Operation ] ________ dest dest [ Function ] •...
Page 118 Chapter 3 Functions Functions Logically OR [ Syntax ] [ Instruction Code/Number of Cycles ] OR.size (:format) src,dest Page= G , S (Can be specified) B , W [ Operation ] dest dest [ Function ] • This instruction logically ORs dest and src together and stores the result in dest . •...
Page 119 Chapter 3 Functions Functions [src/dest Classified by Format] G format dest R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:20[A0] dsp:20[A1] abs20 #IMM...
Page 120 Chapter 3 Functions Functions Restore register/memory [ Syntax ] [ Instruction Code/Number of Cycles ] POP.size (:format) dest Page= 213 G , S (Can be specified) B , W [ Operation ] If the size specifier (.size) is (.B) If the size specifier (.size) is (.W) dest M(SP) dest...
Page 121 Chapter 3 Functions Functions Restore control register POPC POPC POP Control register [ Syntax ] [ Instruction Code/Number of Cycles ] POPC dest Page= 215 [ Operation ] dest M(SP) [ Function ] • This instruction restores from the stack area to the control register indicated by dest . •...
Page 122 Chapter 3 Functions Functions Restore multiple registers POPM POPM POP Multiple [ Syntax ] [ Instruction Code/Number of Cycles ] Page= 215 POPM dest [ Operation ] dest M(SP) *1 Number of registers to be restored [ Function ] • This instruction restores the registers selected by dest collectively from the stack area. •...
Page 123 Chapter 3 Functions Functions Save register/memory/immediate data PUSH PUSH PUSH [ Syntax ] [ Instruction Code/Number of Cycles ] PUSH.size (:format) Page= 216 G , S (Can be specified) B , W [ Operation ] If the size specifier (.size) is (.B) If the size specifier (.size) is (.W) –...
Page 124 Chapter 3 Functions Functions Save effective address PUSHA PUSHA PUSH effective Address [ Syntax ] [ Instruction Code/Number of Cycles ] Page= 218 PUSHA [ Operation ] – M(SP) EVA(src) [ Function ] • This instruction saves the effective address of src to the stack area. [ Selectable src ] R0L/R0 R0H/R1...
Page 125 Chapter 3 Functions Functions Save control register PUSHC PUSHC PUSH Control register [ Syntax ] [ Instruction Code/Number of Cycles ] PUSHC Page= [ Operation ] – M(SP) [ Function ] • This instruction saves the control register indicated by src to the stack area. [ Selectable src ] ISP FLG INTBH INTBL *1 Operation is performed on the stack pointer indicated by the U flag.
Page 126 Chapter 3 Functions Functions Save multiple registers PUSHM PUSHM PUSH Multiple [ Syntax ] [ Instruction Code/Number of Cycles ] PUSHM Page= 219 [ Operation ] – M(SP) *1 Number of registers saved. [ Function ] • This instruction saves the registers selected by src collectively to the stack area. •...
Page 127 Chapter 3 Functions Functions Return from interrupt REIT REIT REturn from InTerrupt [ Syntax ] [ Instruction Code/Number of Cycles ] REIT Page= 219 [ Operation ] M(SP) , FLG M(SP) [ Function ] • This instruction restores the PC and FLG that were saved when an interrupt request was accepted to return from the interrupt handler routine.
Page 128 Chapter 3 Functions Functions Calculate sum-of-products RMPA RMPA Repeat MultiPle & Addition [ Syntax ] [ Instruction Code/Number of Cycles ] RMPA.size Page= 220 B , W [ Operation ] Repeat R2R0(R0) R2R0(R0) M(A0) M(A1) 2 (1) 2 (1) – Until R3 = 0 If you set a value 0 in R3, this instruction is ingored.
Page 129 Chapter 3 Functions Functions Rotate left with carry ROLC ROLC ROtate to Left with Carry [ Syntax ] [ Instruction Code/Number of Cycles ] ROLC.size dest Page= 220 B , W [ Operation ] dest [ Function ] • This instruction rotates dest one bit to the left including the C flag. [ Selectable dest ] dest R0L/R0...
Page 130 Chapter 3 Functions Functions Rotate right with carry RORC RORC ROtate to Right with Carry [ Syntax ] [ Instruction Code/Number of Cycles ] RORC.size dest Page= 221 B , W [ Operation ] dest [ Function ] • This instruction rotates dest one bit to the right including the C flag. [ Selectable dest ] dest R0L/R0...
Page 131 Chapter 3 Functions Functions Rotate ROTate [ Syntax ] [ Instruction Code/Number of Cycles ] ROT.size src,dest Page= 222 B , W [ Operation ] srcÅÉ0 dest srcÅÑ0 [ Function ] • This instruction rotates dest left or right the number of bits indicated by src . The bit overflowing from LSB (MSB) is transferred to MSB(LSB) and the C flag.
Page 132 Chapter 3 Functions Functions Return from subroutine ReTurn from Subroutine [ Syntax ] [ Instruction Code/Number of Cycles ] Page= 223 [ Operation ] M(SP) M(SP) [ Function ] • This instruction causes control to return from a subroutine. [ Flag Change ] Flag Change [ Description Example ]...
Page 133 Chapter 3 Functions Functions Subtract with borrow SuBtract with Borrow [ Instruction Code/Number of Cycles ] [ Syntax ] Page= 224 SBB.size src,dest B , W [ Operation ] dest dest – – [ Function ] • This instruction subtracts src and inverted C flag from dest and stores the result in dest . •...
Page 134 Chapter 3 Functions Functions Subtract & conditional jump SBJNZ SBJNZ SuBtract then Jump on Not Zero [ Syntax ] [ Instruction Code/Number of Cycles ] SBJNZ.size src,dest,label Page= 226 B , W [ Operation ] dest dest – if dest ≠ 0 then jump label [ Function ] •...
Page 135 Chapter 3 Functions Functions Shift arithmetic SHift Arithmetic [ Syntax ] [ Instruction Code/Number of Cycles ] SHA.size src,dest Page= 227 B , W , L [ Operation ] When src < 0 dest When src > 0 dest [ Function ] overflowing from LSB (MSB) is transferred to the C flag.
Page 136 Chapter 3 Functions Functions Shift logical SHift Logical [ Syntax ] [ Instruction Code/Number of Cycles ] SHL.size src,dest Page= 230 B , W , L [ Operation ] dest When src < 0 dest When src > 0 [ Function ] •...
Page 137 Chapter 3 Functions Functions Transfer string backward SMOVB SMOVB String MOVe Backward [ Syntax ] [ Instruction Code/Number of Cycles ] SMOVB.size Page= B , W [ Operation ] When size specifier (.size) is (.B) When size specifier (.size) is (.W) Repeat Repeat M(A1)
Page 138 Chapter 3 Functions Functions Transfer string forward SMOVF SMOVF String MOVe Forward [ Syntax ] [ Instruction Code/Number of Cycles ] SMOVF.size Page= 233 B , W [ Operation ] When size specifier (.size) is (.B) When size specifier (.size) is (.W) Repeat Repeat M(A1)
Page 139 Chapter 3 Functions Functions Store string SSTR SSTR String SToRe [ Syntax ] [ Instruction Code/Number of Cycles ] SSTR.size Page= 233 B , W [ Operation ] When size specifier (.size) is (.B) When size specifier (.size) is (.W) Repeat Repeat M(A1)
Page 140 Chapter 3 Functions Functions Transfer from control register STore from Control register [ Instruction Code/Number of Cycles ] [ Syntax ] Page= 234 src,dest [ Operation ] dest [ Function ] • This instruction transfers the control register indicated by src to dest . If dest is memory, specify the address in which to store the low-order address.
Page 141 Chapter 3 Functions Functions Save context STCTX STCTX STore ConTeXt [ Syntax ] [ Instruction Code/Number of Cycles ] STCTX abs16,abs20 Page= 235 [ Operation ] [ Function ] • This instruction saves task context to the stack area. • Set the RAM address that contains the task number in abs16 and the start address of table data in abs20. •...
Page 142 Chapter 3 Functions Functions Transfer to extended data area STore to EXtra far data area [ Syntax ] [ Instruction Code/Number of Cycles ] STE.size src,dest Page= 235 B , W [ Operation ] dest [ Function ] • This instruction transfers src to dest in an extended area. •...
Page 143 Chapter 3 Functions Functions Conditional transfer STNZ STNZ STore on Not Zero [ Syntax ] [ Instruction Code/Number of Cycles ] STNZ src,dest Page= 237 [ Operation ] if Z = 0 then dest [ Function ] • This instruction transfers src to dest when the Z flag is 0. [ Selectable src/dest ] dest #IMM8...
Page 144 Chapter 3 Functions Functions Conditional transfer STore on Zero [ Syntax ] [ Instruction Code/Number of Cycles ] src,dest Page= 237 [ Operation ] if Z = 1 then dest [ Function ] • This instruction transfers src to dest when the Z flag is 1. [ Selectable src/dest ] dest #IMM8...
Page 145 Chapter 3 Functions Functions Conditional transfer STZX STZX STore on Zero eXtention [ Syntax ] [ Instruction Code/Number of Cycles ] STZX src1,src2,dest Page= [ Operation ] If Z = 1 then dest src1 else dest src2 [ Function ] •...
Page 146 Chapter 3 Functions Functions Subtract without borrow SUBtract [ Syntax ] [ Instruction Code/Number of Cycles ] SUB.size (:format) src,dest Page= 238 G , S (Can be specified) B , W [ Operation ] dest dest – [ Function ] •...
Page 147 Chapter 3 Functions Functions [src/dest Classified by Format] G format dest R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:20[A0] dsp:20[A1] abs20 #IMM...
Page 148 Chapter 3 Functions Functions Test TeST [ Syntax ] [ Instruction Code/Number of Cycles ] TST.size src,dest Page= 241 B , W [ Operation ] dest [ Function ] • Each flag in the flag register changes state depending on the result of logical AND of src and dest . •...
Page 149 Chapter 3 Functions Functions Interrupt for undefined instruction UNDefined instruction [ Syntax ] [ Instruction Code/Number of Cycles ] Page= 243 [ Operation ] – M(SP) , FLG – M(SP) M(FFFDC [ Function ] • This instruction generates an undefined instruction interrupt. •...
Page 150 Chapter 3 Functions Functions Wait WAIT WAIT WAIT [ Syntax ] [ Instruction Code/Number of Cycles ] WAIT Page= 243 [ Operation ] [ Function ] • This instruction halts program execution. Program execution is restarted when an interrupt of a higher priority level than IPL is acknowledged or a reset is generated.
Page 151 Chapter 3 Functions Functions Exchange XCHG XCHG eXCHanGe [ Syntax ] [ Instruction Code/Number of Cycles ] XCHG.size src,dest Page= 244 B , W [ Operation ] dest [ Function ] • This instruction exchanges contents between src and dest . •...
Page 152 Chapter 3 Functions Functions Exclusive OR eXclusive OR [ Syntax ] [ Instruction Code/Number of Cycles ] XOR.size src,dest Page= 245 B , W [ Operation ] dest dest [ Function ] • This instruction exclusive ORs src and dest together and stores the result in dest . •...
Page 153 Chapter 3 Functions Functions...
Page 154: Chapter 4 Instruction Code/Number Of Cycles
Chapter 4 Instruction Code/Number of Cycles 4.1 Guide to This Chapter 4.2 Instruction Code/Number of Cycles...
Page 155: Guide To This Chapter
Chapter 4 Instruction Code Guide to This Chapter 4.1 Guide to This Chapter This chapter describes instruction code and number of cycles for each op-code. The following shows how to read this chapter by using an actual page as an example. Chapter 4 Instruction Code Instruction Code/Number of Cycles LDIPL...
Page 156 Chapter 4 Instruction Code Guide to This Chapter (1) Mnemonic Shows the mnemonic explained in this page. (2) Syntax Shows an instruction syntax using symbols. (3) Instruction code Shows instruction code. Entered in ( ) are omitted depending on src/dest you selected. Contents at addresses following Content at start address (start address of instruction + 2)
Page 157: Instruction Code/Number Of Cycles
Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (1) ABS.size dest dest code b0 b7 dsp8 0 1 1 1 0 1 1 SIZE 1 1 1 1 DEST dsp16/abs16 .size SIZE dest dest DEST DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0 dsp:8[An]...
Page 158 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (2) ADC.size src, dest src code dest code b0 b7 dsp8 dsp8 1 0 1 1 0 0 0 SIZE DEST dsp16/abs16 dsp16/abs16 .size SIZE src/dest SRC/DEST src/dest SRC/DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 159 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles ADCF (1) ADCF.size dest dest code b0 b7 dsp8 0 1 1 1 0 1 1 SIZE 1 1 1 0 DEST dsp16/abs16 .size SIZE dest dest DEST DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 160 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (2) ADD.size:Q #IMM, dest dest code b0 b7 dsp8 1 1 0 0 1 0 0 SIZE IMM4 DEST dsp16/abs16 .size SIZE #IMM IMM4 IMM4 #IMM 0 0 0 0 1 0 0 0 –8 0 0 0 1...
Page 161 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (3) ADD.B:S #IMM8, dest dest code dsp8 #IMM8 1 0 0 0 0 DEST abs16 dest DEST 0 1 1 1 0 0 dsp:8[SB] 1 0 1 dsp:8[SB/FB] dsp:8[FB] 1 1 0 abs16 abs16 1 1 1...
Page 162 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (4) ADD.size:G src, dest src code dest code b0 b7 dsp8 dsp8 1 0 1 0 0 0 0 SIZE DEST dsp16/abs16 dsp16/abs16 .size SIZE src/dest SRC/DEST src/dest SRC/DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 163 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (5) ADD.B:S src, R0L/R0H src code dsp8 0 0 1 0 0 DEST SRC abs16 dest DEST R0L/R0H dsp:8[SB] dsp:8[SB/FB] dsp:8[FB] abs16 abs16 [ Number of Bytes/Number of Cycles ] dsp:8[SB/FB] abs16 Bytes/Cycles...
Page 164 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (7) ADD.size:Q #IMM, SP b0 b7 0 1 1 1 1 1 0 1 1 0 1 1 IMM4 *1 The instruction code is the same regardless of whether you selected (.B) or (.W) for the size specifier (.size). #IMM IMM4 IMM4...
Page 165 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles ADJNZ (1) ADJNZ.size #IMM, dest, label dest code label code b0 b7 dsp8 dsp8 1 1 1 1 1 0 0 SIZE IMM4 DEST dsp16/abs16 dsp8 (label code)= address indicated by label –(start address of instruction + 2) .size SIZE #IMM...
Page 166 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (1) AND.size:G #IMM, dest dest code b0 b7 dsp8 #IMM8 0 1 1 1 0 1 1 SIZE 0 0 1 0 DEST dsp16/abs16 #IMM16 .size SIZE dest dest DEST DEST R0L/R0 0 0 0 0...
Page 167 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (3) AND.size:G src, dest src code dest code b0 b7 1 0 0 1 0 0 0 SIZE DEST dsp8 dsp8 dsp16/abs16 dsp16/abs16 .size SIZE src/dest SRC/DEST src/dest SRC/DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 168 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (4) AND.B:S src, R0L/R0H src code dsp8 0 0 0 1 0 DEST SRC abs16 dest DEST R0L/R0H dsp:8[SB] dsp:8[SB/FB] dsp:8[FB] abs16 abs16 [ Number of Bytes/Number of Cycles ] dsp:8[SB/FB] abs16 Bytes/Cycles...
Page 169 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles BAND (1) BAND src code b0 b7 dsp8 0 1 1 1 1 1 1 0 0 1 0 0 dsp16 bit,R0 0 0 0 0 base:8[A0] 1 0 0 0 base:8[An] bit,R1 0 0 0 1...
Page 170 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles BCLR (2) BCLR:S bit, base:11[SB] dest code dsp8 0 1 0 0 0 [ Number of Bytes/Number of Cycles ] Bytes/Cycles...
Page 171 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles BM Cnd (1) BM Cnd dest dest code b0 b7 dsp8 0 1 1 1 1 1 1 0 0 0 1 0 DEST dsp16 dest dest DEST DEST bit,R0 0 0 0 0 base:8[A0] 1 0 0 0...
Page 172 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles BM Cnd (2) BM Cnd b0 b7 0 1 1 1 1 1 0 1 1 1 0 1 GEU/C 0 0 0 0 0 1 1 1 0 0 0 1 1 0 0 0 EQ/Z 0 0 1 0...
Page 173 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles BNOR (1) BNOR src code b0 b7 dsp8 0 1 1 1 1 1 1 0 0 1 1 1 dsp16 bit,R0 0 0 0 0 base:8[A0] 1 0 0 0 base:8[An] bit,R1 0 0 0 1...
Page 174 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles BNOT (2) BNOT:S bit, base:11[SB] dest code 0 1 0 1 0 dsp8 [ Number of Bytes/Number of Cycles ] Bytes/Cycles BNTST (1) BNTST src code b0 b7 dsp8 0 1 1 1 1 1 1 0 0 0 1 1 dsp16 bit,R0 0 0 0 0...
Page 175 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles BNXOR (1) BNXOR src code b0 b7 dsp8 0 1 1 1 1 1 1 0 1 1 0 1 dsp16 bit,R0 0 0 0 0 base:8[A0] 1 0 0 0 base:8[An] bit,R1 0 0 0 1...
Page 176 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (1) BRK 0 0 0 0 0 0 0 0 [ Number of Bytes/Number of Cycles ] Bytes/Cycles 1/27 *1 If you specify the target address of the BRK interrupt by use of the interrupt table register (INTB), the number of cycles shown in the table increases by two.
Page 177 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles BSET (2) BSET:S bit, base:11[SB] dest code 0 1 0 0 1 dsp8 [ Number of Bytes/Number of Cycles ] Bytes/Cycles BTST (1) BTST:G src src code b0 b7 0 1 1 1 1 1 1 0 1 0 1 1 dsp8 dsp16 bit,R0...
Page 178 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles BTST (2) BTST:S bit, base:11[SB] src code 0 1 0 1 1 dsp8 [ Number of Bytes/Number of Cycles ] Bytes/Cycles BTSTC (1) BTSTC dest dest code b0 b7 dsp8 0 1 1 1 1 1 1 0 0 0 0 0 DEST dsp16...
Page 179 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles BTSTS (1) BTSTS dest dest code b0 b7 0 1 1 1 1 1 1 0 0 0 0 1 DEST dsp8 dsp16 dest dest DEST DEST bit,R0 0 0 0 0 base:8[A0] 1 0 0 0 base:8[An]...
Page 180 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (1) CMP.size:G #IMM, dest dest code b0 b7 dsp8 #IMM8 0 1 1 1 0 1 1 SIZE 1 0 0 0 DEST dsp16/abs16 #IMM16 .size SIZE dest dest DEST DEST R0L/R0 0 0 0 0...
Page 181 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (2) CMP.size:Q #IMM, dest dest code b0 b7 1 1 0 1 0 0 0 SIZE IMM4 DEST dsp8 dsp16/abs16 .size SIZE #IMM IMM4 IMM4 #IMM 0 0 0 0 1 0 0 0 –8 0 0 0 1...
Page 182 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (3) CMP.B:S #IMM8, dest dest code 1 1 1 0 0 DEST #IMM8 dsp8 abs16 dest DEST 0 1 1 1 0 0 dsp:8[SB] 1 0 1 dsp:8[SB/FB] dsp:8[FB] 1 1 0 abs16 abs16 1 1 1...
Page 183 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (4) CMP.size:G src, dest src code dest code b0 b7 dsp8 dsp8 1 1 0 0 0 0 0 SIZE DEST dsp16/abs16 dsp16/abs16 .size SIZE src/dest SRC/DEST src/dest SRC/DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 184 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (5) CMP.B:S src, R0L/R0H src code dsp8 0 0 1 1 1 DEST SRC abs16 dest DEST R0L/R0H dsp:8[SB] dsp:8[SB/FB] dsp:8[FB] abs16 abs16 [ Number of Bytes/Number of Cycles ] dsp:8[SB/FB] abs16 Bytes/Cycles...
Page 185 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles DADC (2) DADC.W #IMM16, R0 b0 b7 0 1 1 1 1 1 0 1 1 1 1 0 1 1 1 0 #IMM16 [ Number of Bytes/Number of Cycles ] Bytes/Cycles DADC (3) DADC.B R0H, R0L...
Page 186 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles DADC (4) DADC.W R1, R0 b0 b7 0 1 1 1 1 1 0 1 1 1 1 0 0 1 1 0 [ Number of Bytes/Number of Cycles ] Bytes/Cycles DADD (1) DADD.B #IMM8, R0L...
Page 187 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles DADD (2) DADD.W #IMM16, R0 b0 b7 #IMM16 0 1 1 1 1 1 0 1 1 1 1 0 1 1 0 0 [ Number of Bytes/Number of Cycles ] Bytes/Cycles DADD (3) DADD.B R0H, R0L...
Page 188 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles DADD (4) DADD.W R1, R0 b0 b7 0 1 1 1 1 1 0 1 1 1 1 0 0 1 0 0 [ Number of Bytes/Number of Cycles ] Bytes/Cycles (1) DEC.B dest...
Page 189 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (2) DEC.W dest 1 1 1 1 DEST 0 1 0 dest DEST [ Number of Bytes/Number of Cycles ] Bytes/Cycles (1) DIV.size #IMM b0 b7 #IMM8 0 1 1 1 1 1 0 SIZE 1 1 1 0 0 0 0 1 #IMM16 .size SIZE...
Page 190 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (2) DIV.size src src code b0 b7 dsp8 0 1 1 1 0 1 1 SIZE 1 1 0 1 dsp16/abs16 .size SIZE R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0 dsp:8[An] R0H/R1 0 0 0 1...
Page 191 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles DIVU (2) DIVU.size src src code b0 b7 dsp8 0 1 1 1 0 1 1 SIZE 1 1 0 0 dsp16/abs16 .size SIZE R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0 dsp:8[An] R0H/R1...
Page 192 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles DIVX (2) DIVX.size src src code b0 b7 dsp8 0 1 1 1 0 1 1 SIZE 1 0 0 1 dsp16/abs16 .size SIZE R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0 dsp:8[An] R0H/R1...
Page 193 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles DSBB (2) DSBB.W #IMM16, R0 b0 b7 #IMM16 0 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 [ Number of Bytes/Number of Cycles ] Bytes/Cycles DSBB (3) DSBB.B R0H, R0L...
Page 194 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles DSBB (4) DSBB.W R1, R0 b0 b7 0 1 1 1 1 1 0 1 1 1 1 0 0 1 1 1 [ Number of Bytes/Number of Cycles ] Bytes/Cycles DSUB (1) DSUB.B #IMM8, R0L...
Page 195 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles DSUB (2) DSUB.W #IMM16, R0 b0 b7 #IMM16 0 1 1 1 1 1 0 1 1 1 1 0 1 1 0 1 [ Number of Bytes/Number of Cycles ] Bytes/Cycles DSUB (3) DSUB.B R0H, R0L...
Page 196 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles DSUB (4) DSUB.W R1, R0 b0 b7 0 1 1 1 1 1 0 1 1 1 1 0 0 1 0 1 [ Number of Bytes/Number of Cycles ] Bytes/Cycles ENTER (1) ENTER...
Page 197 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles EXITD (1) EXITD b0 b7 0 1 1 1 1 1 0 1 1 1 1 1 0 0 1 0 [ Number of Bytes/Number of Cycles ] Bytes/Cycles EXTS (1) EXTS.B dest dest code...
Page 198 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles EXTS (2) EXTS.W R0 b0 b7 0 1 1 1 1 1 0 0 1 1 1 1 0 0 1 1 [ Number of Bytes/Number of Cycles ] Bytes/Cycles FCLR (1) FCLR dest...
Page 199 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles FSET (1) FSET dest b0 b7 1 1 1 0 1 0 1 1 0 DEST 0 1 0 0 dest DEST 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1...
Page 200 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (2) INC.W dest 1 0 1 1 DEST 0 1 0 dest DEST [ Number of Bytes/Number of Cycles ] Bytes/Cycles (1) INT #IMM #IMM 1 1 1 0 1 0 1 1 [ Number of Bytes/Number of Cycles ] Bytes/Cycles 2/19...
Page 201 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles INTO (1) INTO 1 1 1 1 0 1 1 0 [ Number of Bytes/Number of Cycles ] Bytes/Cycles *1 If the O flag = 1, the number of cycles above is increased by 19. J Cnd (1) J Cnd label...
Page 202 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles J Cnd (2) J Cnd label label code b0 b7 dsp8 0 1 1 1 1 1 0 1 1 1 0 0 dsp8 =address indicated by label – (start address of instruction + 2) 1 0 0 0 1 1 0 0 1 0 0 1...
Page 203 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (2) JMP.B label label code dsp8 1 1 1 1 1 1 1 0 dsp8 = address indicated by label – (start address of instruction + 1) [ Number of Bytes/Number of Cycles ] Bytes/Cycles (3) JMP.W label...
Page 204 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (4) JMP.A label label code abs20 1 1 1 1 1 1 0 0 [ Number of Bytes/Number of Cycles ] Bytes/Cycles JMPI (1) JMPI.W src code b0 b7 dsp8 0 1 1 1 1 1 0 1 0 0 1 0 dsp16/abs16 dsp20...
Page 205 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles JMPI (2) JMPI.A src code b0 b7 dsp8 0 1 1 1 1 1 0 1 0 0 0 0 dsp16/abs16 dsp20 dsp:8[A0] 0 0 0 0 1 0 0 0 R2R0 dsp:8[An] dsp:8[A1]...
Page 206 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (1) JSR.W label label code dsp16 1 1 1 1 0 1 0 1 dsp16 = address indicated by label – (start address of instruction + 1) [ Number of Bytes/Number of Cycles ] Bytes/Cycles (2) JSR.A label...
Page 207 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles JSRI (1) JSRI.W src code b0 b7 dsp8 0 1 1 1 1 1 0 1 0 0 1 1 dsp16/abs16 dsp20 dsp:8[A0] 0 0 0 0 1 0 0 0 dsp:8[An] dsp:8[A1] 0 0 0 1...
Page 208 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles JSRS (1) JSRS #IMM8 #IMM8 1 1 1 0 1 1 1 1 [ Number of Bytes/Number of Cycles ] Bytes/Cycles 2/13 (1) LDC #IMM16, dest b0 b7 #IMM16 1 1 1 0 1 0 1 1 0 DEST 0 0 0 0 dest...
Page 209 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (2) LDC src, dest src code b0 b7 dsp8 0 1 1 1 1 0 1 0 1 DEST dsp16/abs16 dest DEST 0 0 0 0 dsp:8[A0] 1 0 0 0 0 0 0 dsp:8[An] 0 0 0 1...
Page 210 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (1) LDE.size abs20, dest src code dest code b0 b7 abs20 dsp8 0 1 1 1 0 1 0 SIZE 1 0 0 0 DEST dsp16/abs16 .size SIZE dest dest DEST DEST R0L/R0...
Page 211 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (3) LDE.size [A1A0], dest dest code b0 b7 dsp8 0 1 1 1 0 1 0 SIZE 1 0 1 0 DEST dsp16/abs16 .size SIZE dest dest DEST DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 212 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles LDIPL (1) LDIPL #IMM b0 b7 0 1 1 1 1 1 0 1 1 0 1 0 #IMM [ Number of Bytes/Number of Cycles ] Bytes/Cycles (1) MOV.size:G #IMM, dest dest code b0 b7 dsp8...
Page 213 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (2) MOV.size:Q #IMM, dest dest code b0 b7 1 1 0 1 1 0 0 SIZE IMM4 DEST dsp8 dsp16/abs16 .size SIZE #IMM IMM4 IMM4 #IMM 0 0 0 0 1 0 0 0 –8 0 0 0 1...
Page 214 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (3) MOV.B:S #IMM8, dest dest code 1 1 0 0 0 DEST #IMM8 dsp8 abs16 dest DEST 0 1 1 1 0 0 dsp:8[SB] 1 0 1 dsp:8[SB/FB] dsp:8[FB] 1 1 0 abs16 abs16 1 1 1...
Page 215 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (4) MOV.size:S #IMM, dest #IMM8 1 SIZE 1 0 DEST 0 1 0 #IMM16 .size SIZE dest DEST [ Number of Bytes/Number of Cycles ] Bytes/Cycles *1 If the size specifier (.size) is (.W), the number of bytes and cycles above are increased by 1 and 1, respectively.
Page 216 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (6) MOV.size:G src, dest src code dest code b0 b7 dsp8 dsp8 0 1 1 1 0 0 1 SIZE DEST dsp16/abs16 dsp16/abs16 .size SIZE src/dest SRC/DEST src/dest SRC/DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 217 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (7) MOV.B:S src, dest src code 0 0 1 1 0 DEST SRC dsp8 abs16 dest DEST R0L/R0H dsp:8[SB] dsp:8[SB/FB] dsp:8[FB] abs16 abs16 [ Number of Bytes/Number of Cycles ] dsp:8[SB/FB] abs16 Bytes/Cycles...
Page 218 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (9) MOV.B:S src, R0L/R0H src code 0 0 0 0 1 DEST SRC dsp8 abs16 dest DEST R0L/R0H dsp:8[SB] dsp:8[SB/FB] dsp:8[FB] abs16 abs16 [ Number of Bytes/Number of Cycles ] dsp:8[SB/FB] abs16 Bytes/Cycles...
Page 219 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (11) MOV.size:G src, dsp:8[SP] src code dest code b0 b7 dsp8 dsp8 0 1 1 1 0 1 0 SIZE 0 0 1 1 dsp16/abs16 .size SIZE R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0 dsp:8[An]...
Page 220 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles MOV Dir (1) MOV Dir R0L, dest dest code b0 b7 dsp8 0 1 1 1 1 1 0 0 1 0 DIR DEST dsp16/abs16 dest dest DEST DEST dsp:8[A0] 0 0 0 0 1 0 0 0 dsp:8[An]...
Page 221 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles MOV Dir (2) MOV Dir src, R0L dest code b0 b7 dsp8 0 1 1 1 1 1 0 0 0 0 DIR dsp16/abs16 dsp:8[A0] 0 0 0 0 1 0 0 0 dsp:8[An] dsp:8[A1] 0 0 0 1...
Page 222 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (1) MUL.size #IMM, dest dest code b0 b7 dsp8 #IMM8 0 1 1 1 1 1 0 SIZE 0 1 0 1 DEST dsp16/abs16 #IMM16 .size SIZE dest dest DEST DEST R0L/R0 0 0 0 0...
Page 223 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (2) MUL.size src, dest src code dest code b0 b7 dsp8 dsp8 0 1 1 1 1 0 0 SIZE DEST dsp16/abs16 dsp16/abs16 .size SIZE R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0 dsp:8[An]...
Page 224 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles MULU (1) MULU.size #IMM, dest dest code b0 b7 dsp8 #IMM8 0 1 1 1 1 1 0 SIZE 0 1 0 0 DEST dsp16/abs16 #IMM16 .size SIZE dest dest DEST DEST R0L/R0...
Page 225 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles MULU (2) MULU.size src, dest src code dest code b0 b7 dsp8 dsp8 0 1 1 1 0 0 0 SIZE DEST dsp16/abs16 dsp16/abs16 .size SIZE R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0 dsp:8[An]...
Page 226 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (1) NEG.size dest dest code b0 b7 dsp8 0 1 1 1 0 1 0 SIZE 0 1 0 1 DEST dsp16/abs16 .size SIZE dest dest DEST DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0 dsp:8[An]...
Page 227 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (1) NOT.size:G dest dest code b0 b7 dsp8 0 1 1 1 0 1 0 SIZE 0 1 1 1 DEST dsp16/abs16 .size SIZE dest dest DEST DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0 dsp:8[An]...
Page 228 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (1) OR.size:G #IMM, dest dest code b0 b7 dsp8 #IMM8 0 1 1 1 0 1 1 SIZE 0 0 1 1 DEST dsp16/abs16 #IMM16 .size SIZE dest dest DEST DEST R0L/R0 0 0 0 0...
Page 229 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (3) OR.size:G src, dest src code dest code b0 b7 dsp8 dsp8 1 0 0 1 1 0 0 SIZE DEST dsp16/abs16 dsp16/abs16 .size SIZE src/dest SRC/DEST src/dest SRC/DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 230 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (4) OR.B:S src, R0L/R0H dest code dsp8 0 0 0 1 1 DEST SRC abs16 dest DEST R0L/R0H dsp:8[SB] dsp:8[SB/FB] dsp:8[FB] abs16 abs16 [ Number of Bytes/Number of Cycles ] dsp:8[SB/FB] abs16 Bytes/Cycles...
Page 231 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (2) POP.B:S dest 1 0 0 1 DEST 0 1 0 dest DEST [ Number of Bytes/Number of Cycles ] Bytes/Cycles (3) POP.W:S dest 1 1 0 1 DEST 0 1 0 dest DEST [ Number of Bytes/Number of Cycles ]...
Page 232 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles POPC (1) POPC dest b0 b7 1 1 1 0 1 0 1 1 0 DEST 0 0 1 1 dest DEST dest DEST 0 0 0 1 0 0 INTBL 0 0 1 1 0 1...
Page 233 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles PUSH (1) PUSH.size:G #IMM b0 b7 #IMM8 0 1 1 1 1 1 0 SIZE 1 1 1 0 0 0 1 0 #IMM16 .size SIZE [ Number of Bytes/Number of Cycles ] Bytes/Cycles *1 If the size specifier (.size) is (.W), the number of bytes above is increased by 1.
Page 234 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles PUSH (3) PUSH.B:S 1 0 0 0 SRC 0 1 0 [ Number of Bytes/Number of Cycles ] Bytes/Cycles PUSH (4) PUSH.W:S 1 1 0 0 SRC 0 1 0 [ Number of Bytes/Number of Cycles ] Bytes/Cycles...
Page 235 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles PUSHA (1 ) PUSHA src src code b0 b7 dsp8 0 1 1 1 1 1 0 1 1 0 0 1 dsp16/abs16 dsp:8[A0] 1 0 0 0 dsp:8[An] dsp:8[A1] 1 0 0 1 dsp:8[SB] 1 0 1 0...
Page 236 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles PUSHM (1) PUSHM 1 1 1 0 1 1 0 0 R0 R1 A0 A1 SB FB *1 The bit for a selected register is 1. The bit for a non-selected register is 0. [ Number of Bytes/Number of Cycles ] Bytes/Cycles 2/2 m...
Page 237 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles RMPA (1) RMPA.size b0 b7 0 1 1 1 1 1 0 SIZE 1 1 1 1 0 0 0 1 .size SIZE [ Number of Bytes/Number of Cycles ] 2/4+7 Bytes/Cycles *1 m denotes the number of operation performed.
Page 238 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles RORC (1) RORC.size dest dest code b0 b7 dsp8 0 1 1 1 0 1 1 SIZE 1 0 1 1 DEST dsp16/abs16 .size SIZE dest dest DEST DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 239 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (1) ROT.size #IMM, dest dest code b0 b7 dsp8 1 1 1 0 0 0 0 SIZE IMM4 DEST dsp16/abs16 .size SIZE #IMM IMM4 IMM4 #IMM 0 0 0 0 1 0 0 0 –1 0 0 0 1...
Page 240 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (2) ROT.size R1H, dest dest code b0 b7 dsp8 0 1 1 1 0 1 0 SIZE 0 1 1 0 DEST dsp16/abs16 .size SIZE dest dest DEST DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 241 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (1) SBB.size #IMM, dest dest code b0 b7 dsp8 #IMM8 0 1 1 1 0 1 1 SIZE 0 1 1 1 DEST dsp16/abs16 #IMM16 .size SIZE dest dest DEST DEST R0L/R0 0 0 0 0...
Page 242 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (2) SBB.size src, dest src code dest code b0 b7 dsp8 dsp8 1 0 1 1 1 0 0 SIZE DEST dsp16/abs16 dsp16/abs16 .size SIZE src/dest SRC/DEST src/dest SRC/DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 243 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles SBJNZ (1) SBJNZ.size #IMM, dest, label dest code label code b0 b7 dsp8 dsp8 1 1 1 1 1 0 0 SIZE IMM4 DEST dsp16/abs16 dsp8(label code) = address indicated by label – (start address of instruction + 2) .size SIZE #IMM...
Page 244 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (1) SHA.size #IMM, dest dest code b0 b7 dsp8 1 1 1 1 0 0 0 SIZE IMM4 DEST dsp16/abs16 .size SIZE #IMM IMM4 IMM4 #IMM 0 0 0 0 1 0 0 0 –1 0 0 0 1...
Page 245 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (2) SHA.size R1H, dest dest code b0 b7 0 1 1 1 0 1 0 SIZE 1 1 1 1 DEST dsp8 dsp16/abs16 .size SIZE dest dest DEST DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 246 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (4) SHA.L R1H, dest b0 b7 1 1 1 0 1 0 1 1 0 0 1 DEST 0 0 0 1 dest DEST R2R0 R3R1 [ Number of Bytes/Number of Cycles ] Bytes/Cycles 2/4+m *1 m denotes the number of shifts performed.
Page 247 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (1) SHL.size #IMM, dest dest code b0 b7 1 1 1 0 1 0 0 SIZE IMM4 DEST dsp8 dsp16/abs16 .size SIZE #IMM IMM4 IMM4 #IMM 0 0 0 0 1 0 0 0 –1 0 0 0 1...
Page 248 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (2) SHL.size R1H, dest dest code b0 b7 dsp8 0 1 1 1 0 1 0 SIZE 1 1 1 0 DEST dsp16/abs16 .size SIZE dest dest DEST DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 249 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (4) SHL.L R1H, dest b0 b7 1 1 1 0 1 0 1 1 0 0 0 DEST 0 0 0 1 dest DEST R2R0 R3R1 [ Number of Bytes/Number of Cycles ] Bytes/Cycles 2/4+m *1 m denotes the number of shifts performed.
Page 250 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles SMOVF (1) SMOVF.size b0 b7 0 1 1 1 1 1 0 SIZE 1 1 1 0 1 0 0 0 .size SIZE [ Number of Bytes/Number of Cycles ] Bytes/Cycles 2/5+5 *1 m denotes the number of transfers performed.
Page 251 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (1) STC src, dest dest Code b0 b7 dsp8 0 1 1 1 1 0 1 1 1 DEST dsp16/abs16 dest DEST dest DEST 0 0 0 0 0 0 0 dsp:8[A0] 1 0 0 0 dsp:8[An]...
Page 252 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles STCTX (1) STCTX abs16, abs20 b0 b7 abs16 abs20 0 1 1 1 1 1 0 1 1 1 1 1 0 0 0 0 [ Number of Bytes/Number of Cycles ] Bytes/Cycles 7/11+2 *1 m denotes the number of transfers performed.
Page 253 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (2) STE.size src, dsp:20[A0] src code dest code b0 b7 dsp8 dsp20 0 1 1 1 0 1 0 SIZE 0 0 0 1 dsp16/abs16 .size SIZE R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0 dsp:8[An]...
Page 254 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles STNZ (1) STNZ #IMM8, dest dest code #IMM8 dsp8 1 1 0 1 0 DEST abs16 dest DEST 0 1 1 1 0 0 dsp:8[SB] 1 0 1 dsp:8[SB/FB] dsp:8[FB] 1 1 0 abs16 abs16...
Page 255 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles STZX (1) STZX #IMM8 , #IMM8 , dest dest code #IMM82 1 1 0 1 1 DEST #IMM81 dsp8 abs16 dest DEST 0 1 1 1 0 0 dsp:8[SB] 1 0 1 dsp:8[SB/FB] dsp:8[FB] 1 1 0...
Page 256 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (2) SUB.B:S #IMM8, dest dest code #IMM8 1 0 0 0 1 DEST dsp8 abs16 dest DEST 0 1 1 1 0 0 dsp:8[SB] 1 0 1 dsp:8[SB/FB] dsp:8[FB] 1 1 0 abs16 abs16 1 1 1...
Page 257 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (3) SUB.size:G src, dest src code dest code b0 b7 dsp8 dsp8 1 0 1 0 1 0 0 SIZE DEST dsp16/abs16 dsp16/abs16 .size SIZE src/dest SRC/DEST src/dest SRC/DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 258 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (4) SUB.B:S src, R0L/R0H dest code dsp8 0 0 1 0 1 DEST SRC abs16 dest DEST R0L/R0H dsp:8[SB] dsp:8[SB/FB] dsp:8[FB] abs16 abs16 [ Number of Bytes/Number of Cycles ] dsp:8[SB/FB] abs16 Bytes/Cycles...
Page 259 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (2) TST.size src, dest src code dest code b0 b7 dsp8 dsp8 1 0 0 0 0 0 0 SIZE DEST dsp16/abs16 dsp16/abs16 .size SIZE src/dest SRC/DEST src/dest SRC/DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 260 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (1) UND 1 1 1 1 1 1 1 1 [ Number of Bytes/Number of Cycles ] 1/20 Bytes/Cycles WAIT (1) WAIT b0 b7 0 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 [ Number of Bytes/Number of Cycles ] Bytes/Cycles...
Page 261 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles XCHG (1) XCHG.size src, dest dest code b0 b7 dsp8 0 1 1 1 1 0 1 SIZE 0 0 SRC DEST dsp16/abs16 .size SIZE R0L/R0 R0H/R1 R1L/R2 R1H/R3 dest DEST dest DEST...
Page 262 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (1) XOR.size #IMM, dest dest code b0 b7 dsp8 #IMM8 0 1 1 1 0 1 1 SIZE 0 0 0 1 DEST dsp16/abs16 #IMM16 .size SIZE dest dest DEST DEST R0L/R0 0 0 0 0...
Page 263 Chapter 4 Instruction Code/Number of Cycles Instruction Code/Number of Cycles (2) XOR.size src, dest src code dest code b0 b7 dsp8 dsp8 1 0 0 0 1 0 0 SIZE DEST dsp16/abs16 dsp16/abs16 .size SIZE src/dest SRC/DEST src/dest SRC/DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 264: Chapter 5 Interrupt
Chapter 5 Interrupt 5.1 Outline of Interrupt 5.2 Interrupt Control 5.3 Interrupt Sequence 5.4 Return from Interrupt Routine 5.5 Interrupt Priority 5.6 Multiple Interrupts 5.7 Precautions for Interrupts...
Page 265: Outline Of Interrupt
Chapter 5 Interrupt 5.1 Outline of Interrupt 5.1 Outline of Interrupt When an interrupt request is acknowledged, control branches to the interrupt routine that is set to an inter- rupt vector table. Each interrupt vector table must have had the start address of its corresponding interrupt routine set.
Page 266 Chapter 5 Interrupt 5.1 Outline of Interrupt 5.1.2 Software Interrupts Software interrupts are generated by some instruction that generates an interrupt request when ex- ecuted. Software interrupts are nonmaskable interrupts. (1) Undefined-instruction interrupt This interrupt occurs when the UND instruction is executed. (2) Overflow interrupt This interrupt occurs if the INTO instruction is executed when the O flag is 1.
Page 267 Chapter 5 Interrupt 5.1 Outline of Interrupt 5.1.3 Hardware Interrupts There are Two types in hardware Interrupts; special interrupts and Peripherai I/O interrupts. (1) Special interrupts Special interrupts are nonmaskable interrupts. • Reset ____________ A reset occurs when the RESET pin is pulled low. ______ •...
Page 268: Interrupt Control
Chapter 5 Interrupt 5.2 Interrupt Control 5.2 Interrupt Control The following explains how to enable/disable maskable interrupts and set acknowledge priority. The expla- nation here does not apply to non-maskable interrupts. Maskable interrupts are enabled and disabled by using the interrupt enable flag (I flag), interrupt priority level select bit, and processor interrupt priority level (IPL).
Page 269 M16C/60, M16C/61 group, and M16C/20 series: two clock M16C/60 series after M16C/62 group (it has M16C/62 group) : three clock...
Page 270 Chapter 5 Interrupt 5.2 Interrupt Control 5.2.4 Rewrite the interrupt control register To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled.
Page 271: Interrupt Sequence
Chapter 5 Interrupt 5.3 Interrupt Sequence 5.3 Interrupt Sequence An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle.
Page 272 Chapter 5 Interrupt 5.3 Interrupt Sequence 5.3.1 Interrupt Response Time The interrupt response time means a period of time from when an interrupt request is generated till when the first instruction of the interrupt routine is executed. This period consists of time (a) from when an interrupt request is generated to when the instruction then under way is completed and time (b) in which an interrupt sequence is executed.
Page 273 Chapter 5 Interrupt 5.3 Interrupt Sequence 5.3.2 Changes of IPL When Interrupt Request Acknowledged When an interrupt request is acknowledged, the interrupt priority level of the acknowledged interrupt is set to the processor interrupt priority level (IPL). If an interrupt request is acknowledged that does not have an interrupt priority level, the value shown in Table 5.3.2 is set to the IPL.
Page 274 Chapter 5 Interrupt 5.3 Interrupt Sequence The register save operation performed in an interrupt sequence differs depending on whether the con- tent of the stack pointer (SP) is an even or an odd number when an interrupt request is acknowledged. If the stack pointer (SP) indicates an even number, the contents of the flag register (FLG) and program counter (PC) each are saved simultaneously all 16 bits together.
Page 275: Return From Interrupt Routine
Chapter 5 Interrupt 5.4 Return from Interrupt Routine 5.4 Return from Interrupt Routine As you execute the REIT instruction at the end of the interrupt routine, the contents of the flag register (FLG) and program counter (PC) that have been saved to the stack area immediately preceding the inter- rupt sequence are automatically restored.
Page 276: Interrupt Priority
Chapter 5 Interrupt 5.5 Interrupt Priority 5.5 Interrupt Priority If two or more interrupt requests are sampled active at the same time, whichever interrupt request is ac- knowledged that has the highest priority. Maskable interrupts (Peripheral I/O interrupts) can be assigned any desired priority by setting the interrupt priority level select bit accordingly.
Page 277: Multiple Interrupts
Chapter 5 Interrupt 5.6 Multiple interrupts 5.6 Multiple Interrupts The following shows the internal bit states when control has branched to an interrupt routine: • The interrupt enable flag (I flag) is cleared to 0 (interrupts disabled). • The interrupt request bit for the acknowledged interrupt is cleared to 0. •...
Page 278 Chapter 5 Interrupt 5.6 Multiple interrupts Interrupt request Nesting generated Reset Main routine Time I = 0 IPL = 0 Interrupt 1 I = 1 Interrupt priority level = 3 Interrupt 1 I = 0 IPL = 3 Interrupt 2 Multiple interrupts I = 1 Interrupt priority level = 5...
Page 279: Precautions For Interrupts
Chapter 5 Interrupt 5.7 Precautions for Interrupts (1) Reading address 00000 • When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 00000 will then be set to “0”.
Page 280 Q & A Information in a Q&A form to be used to make the most of the M16C family is given below. Usually, one question and the answer to it are given on one page; the upper section is for the question, and the lower section is for the answer (if a pair of question and answer extends over two or more pages, a page number is given at the lower-right corner).
Page 281 How do I distinguish between the static base register (SB) and the frame base register (FB)? SB and FB function in the same manner, so you can use them as intended in programming in the assembly language. If you write a program in C, use FB as a stack frame base register. Q&A-2...
Page 282 Interrupt Is it possible to change the value of the interrupt table register (INTB) while a program is being executed? Yes. But there can be a chance that the microcomputer runs away out of control if an interrupt request occurs in changing the value of INTB. So it is not recommended to frequently change the value of INTB while a program is being executed.
Page 283 What is the difference between the user stack pointer (USP) and the interrupt stack pointer (ISP)?, What are their roles? You use USP when using the OS. When several tasks run, the OS secures stack areas to save registers of individual tasks. Also, stack areas have to be secured, task by task, to be used for handling interrupts that occur while tasks are being executed.
Page 284 How does the instruction code become if I use a bit instruction in absolute addressing ? An explanation is given here by taking BSET bit,base:16 as an example. This instruction is a 4-byte instruction. The 2 higher-order bytes of the instruction code indicate operation code, and the 2 lower-order bytes make up addressing mode to expresse bit,base:16.
Page 285 What is the difference between the DIV instruction and the DIVX instruction? Either of the DIV instruction and the DIVX instruction is an instruction for signed division, the sign of the remainder is different. The sign of the remainder left after the DIV instruction is the same as that of the dividend, on the contrary, the sign of the remainder of the DIVX instruction is the same as that of the divisor.
Page 286 Glossary Technical terms used in this software manual are explained below. They are good in this manual only. Glossary-1...
Page 287 An after-modification address to be actually used. extention area For the M16C/60 series and M16C/20 series, the area from 10000 through FFFFF Abbreviation for Least Significant Biit The bit occupying the lowest-order position of a data item.
Page 288 Term Meaning Related word macro instruction An instruction, written in a source language, to be expressed in a number of machine instructions when compiled into a machine code program. Abbreviation for Most Significant Bit The bit occupying the highest-order position of a data item.
Page 289 Term Meaning Related word shift out To move the content of a register either to the right or left until fully overflowed. sign bit A bit that indicates either a positive or a negative (the highest-order bit). sign extension To extend a data length in which the higher-order to be extended are made to have the same sign of the sign bit.
Page 290 Table of symbols Symbols used in this software manual are explained below. They are good in this manual only. Symbol-1...
Page 291 Symbol Meaning Transposition from the right side to the left side Interchange between the right side and the left side Addition Subtraction Multiplication Division Logical conjunction Logical disjunction Exclusive disjunction Logical negation dsp16 16-bit displacement dsp20 20-bit displacement dsp8 8-bit displacement EVA( ) An effective address indicated by what is enclosed in (Å@) EXT( )
Page 292 Index Frame base register ••• 5 Function ••• 37 A0 and A1 ••• 5 A1A0 ••• 5 Address register ••• 5 Interrupt table register ••• 5 Address space ••• 3 I flag ••• 6 Addressing mode ••• 22 Instruction code ••• 139 Instruction Format •••...
Page 293 Operation ••• 37 Static base register ••• 5 Overflow flag ••• 6 String ••• 15 Syntax ••• 35, 38 PC ••• 5 Processor interrupt priority level ••• 7 U flag ••• 6 Program counter ••• 5 User stack pointer ••• 5 USP •••...
Page 294 SOFTWARE MANUAL M16C/60 Series, M16C/20 Series Jun. First Edition 1998 Editioned by Committee of editing of Mitsubishi System LSI design Corporation Published by Mitsubishi Electric Corp., Kitaitami Works This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation.

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Mitsubishi M16C/60 Series Software Manual

Chapter 1 Overview

Chapter 2 Addressing Modes

Chapter 3 Functions

Chapter 4 Instruction Code/Number of Cycles

Chapter 5 Interrupt

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