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[T=1]
[T=1]
∆
Instructions
:
ADC
∆
AND
∆
EOR
∆
ORA
∆
SBC
Byte length
:
3
Cycle number
:
8
Timing
:
φ
SYNC
R/W
RD
WR
ADDR
PC
DATA
Op -code
ADDR
H
PC
H
ADDR
L
O p -
PC
L
/DATA
code
C : C arry of AD
+X or Y
L
164
ABSOLUTE X, ABSOLUTE Y
∆
$hhll,X or Y
(T=1)
∆
$hhll,X or Y
(T=1)
∆
$hhll,X or Y
(T=1)
∆
$hhll,X or Y
(T=1)
∆
$hhll,X or Y
(T=1)
PC +1
PC +2
AD
AD
H
L
PC
PC
H
H
AD
AD
AD
PC
+1
L
PC
+2
H
L
L
A D
+X(or Y )
A D
+X(or Y )
L
L
A D
A D
+C
H
H
DATA
Invalid
1
AD
+C
AD
H
H
+X
AD
+X
L
DA TA
L
(or Y)
(or Y)
1
X,00
DATA
Invalid
2
00
DA TA
X
X
X
2
NEW
DATA
NEW
DA TA
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