Table of Contents
Advertisement
[T=1]
[T=1]
∆
Instructions
:
ADC
∆
AND
∆
EOR
∆
ORA
∆
SBC
Byte length
:
3
Cycle number
:
7
Timing
:
φ
SYNC
R/W
RD
WR
ADDR
PC
DATA
ADDR
H
PC
H
ADDR
L
PC
L
/DATA
code
ABSOLUTE
∆
$hhll
(T=1)
∆
$hhll
(T=1)
∆
$hhll
(T=1)
∆
$hhll
(T=1)
∆
$hhll
(T=1)
PC +2
PC +1
AD
Op -code
L
PC
PC
H
H
O p -
AD
AD
PC
+1
PC
+2
L
L
L
AD
L
AD
H
DATA
AD
H
1
AD
H
DA TA
DA TA
AD
X
H
L
1
2
X,00
DATA
Invalid
2
00
NEW
X
X
DA TA
NEW
DATA
161
Advertisement
Table of Contents
