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AC C UM ULATOR BIT RELATIV E
∆
Instructions
:
∆
Byte length
:
2
(2) With branch
Cycle number
:
6
Timing
:
φ
SYNC
R/W
RD
WR
ADDR
DATA
ADDR
H
ADDR
L
PC
/DATA
RR : Offset address
* 1 : (PC +1)
L
* 2 : ((PC +2) ± RR)
118
∆
BBC
i,A,$hhll
∆
BBS
i,A,$hhll
PC
Op -code
PC
H
In-
O p -
L
PC
+1
L
valid
code
L
PC +1
Invalid
PC
H
In-
± RR
PC
+1
PC
+1
L
L
valid
(PC+2)
((PC+2) ± RR)
L
(PC+1)
(PC+2)
H
H
Invalid
± RR
(PC +2)
(PC +2)
H
* 2
* 1
(PC+2)
L
± RR
Invalid
((PC+2) ± RR
H
)H
* 2
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