Appendix 1. Instruction Cycles In Each Addressing Mode - Mitsubishi M16C/60 Series Software Manual

APPENDIX 1

APPENDIX 1. Instruction Cycles in each Addressing Mode

Clock φ controls the system timing of 740 Family. The SYNC signal and the value of PC
(Program Counter) are output in every instruction fetch cycle. The Op-Code is fetched during
the next half-period of φ . The instruction decoder of CPU decodes this Op-Code and
determines the following how to execute the instruction. The instruction timings of all address-
ing modes are described on the following pages.
In these figures, φ , SYNC, R/W (RD, WR), ADDR (ADDR
signals of the single-chip microcomputer; therefore, these signals can be investigated only in
the microprocessor mode.
The combination of these signals differs according to the microcomputer's type. The following
table lists the valid signal for each product.
Valid signal for each product
Type
M507XX
M509XX
M374XX
(Except M37451)
M38XXX
M375XX
M37451
M50734
Instruction Cycles in each Addressing Mode
φ
R/W
SYNC
, ADDR
L
W ADDR DATA ADDR
R
), and DATA are internal
H
ADDR /DATA
H L
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