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∆
Instruction
:
STA
Byte length
:
2
Cycle number
:
7
Timing
:
φ
SYNC
R/W
RD
WR
ADDR
PC
DATA
Op -code
ADDR
H
PC
H
ADDR
L
O p -
PC
L
/DATA
code
BA : Basic address
IN D IREC T X
∆
($zz,X)
(PC +1)
L
PC +1
,00
BA
Invalid
L
PC
H
(PC
BA
PC
+1
L
L
+1)
L
B A
+X
L
B A
+X+1
L
,00
,00
AD
AD
L
00
BA
L
AD
AD
BA
+X
L
H
L
+X+1
AD
L
AD
H
Invalid
DATA
H
AD
H
AD
AD
L
DATA
L
145
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