Appendix 4 Internal Control Cycle And Response Delay Time - Mitsubishi NZ2GFCF-D62PD2 User Manual

Appendix 4
For the high-speed counter module, responses are delayed by the causes shown in (1) to (3).
(1) Scan time of the program in the master station (SM)
This scan time causes delays of remote I/O signals, remote registers, and remote buffer memory.
(2) Link scan time (LS)
This is the time taken for sending data from each station on the network and finishing the one cycle.
For details, refer to the following.
User's manual for the master/local module used
(3) Control cycle of the high-speed counter module (ΔT
Up to ΔT (ΔT ×2) delay occurs until the high-speed counter module completes processing after the module
1 2
reads remote output signals, remote registers, and remote buffer memory updated by the program.
In addition, the update timing of remote input signals, remote registers, and remote buffer memory fluctuates
within one control cycle.
Abbreviation
Indicates the maximum delay time of internal processing. (ΔT
ΔT
1
Link scan time is not included in ΔT
Internal control cycle time (0.5ms)
ΔT
2
Link scan time is not included in ΔT
Processing time for acquiring data for the maximum setting number of
ΔT
3
steps of cam switches (16 points × 16 steps) and analyzing them (40ms)
Internal Control Cycle and Response Delay
Time
Description
.
1
.
2
)
2
Remarks
× 2).
2
⎯
⎯
The smaller the number of steps, the
shorter the processing time.
APPENDICES
A
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