NAiS FP Series Hardware Manual page 167

System Registers
Address
Input 402
setting
403
404 to
407
Notes
With the NPST–GR, "0" or "1" is set for each bit on the screen
in the setting for system register 403.
If system register 400 to 403 are set simultaneously for the
same input relay, the following precedence order is effective:
A-12
Name of system register
Pulse catch input function
settings
Interrupt input settings
Unused
Default
Set value (parameter)
value
H0 X5 X4 X3 X2 X1 X0
0 0 0 0 0 0
In FPWIN Pro, select items from the menu.
In FP Programmer II, enter the above set-
tings in hexadecimal.
When X3 and X4 are set to pulse catch input
15
402:
In the case of FP0, settings X6 and X7 are
invalid.
H0 Using NPST–GR ver. 4
X5 X4 X3 X2 X1 X0
(0: Standard input/1: Interrupt input)
X5 X4 X3 X2 X1 X0
(When 0: on/When 1: off)
In FPWIN Pro, select items from the menu.
FP programmer II:
When setting inputs X0, X1, X2, and X3 as
interrupts, and X0 and X1 are set as interrupt
inputs when going from on to off.
Specify
edge
15
403:
H0
With the FP0, values set with the program-
ming tool become invalid.
Matsushita Electric Works (Europe) AG
FP0 Hardware
0: Standard input
1: Pulse catch input
0
0 0 0 1 1 0 0 0
X5 X4 X3 X2 X1 X0
H1 H8
Input H18
Specify the input con-
tacts used as interrupt
inputs in the upper
byte.
Specify the effective
interrupt edge in the
lower byte.
Specify
interrupt
0 0 0 0 1 1 0 0 1 1 1 1
X5 X4 X3 X2 X1 X0 X5 X4 X3 X2 X1 X0
H3 H0 HF
Input H30F
0