Starting The Superclock-2 Module - Xilinx Virtex UltraScale FPGA VCU1287 Getting Started Manual

Figure 1-22 shows the VCU1287 board with the cable connections required for the Quad
124 GTY IBERT demonstration.
X-Ref Target - Figure 1-22
Figure 1-22: Cable Connections for Quad 124 GTY IBERT Demonstration

Starting the SuperClock-2 Module

The SuperClock-2 module provides LVDS clock outputs for the GTH and GTY transceivers
reference clock in the IBERT demonstration. For both of the GTH and GTY IBERT
demonstrations, the output clock frequency is preset to 125.00 MHz. See the description for
Starting the SuperClock-2 Module, page
VCU1287 IBERT Getting Started Guide
UG1203 (v2016.4) December 15. 2016
Chapter 1: VCU1287 IBERT Getting Started Guide
13, for more details.
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