Starting The Superclock-2 Module - Xilinx Virtex UltraScale FPGA VCU1287 Getting Started Manual

Starting the SuperClock-2 Module

The SuperClock-2 module features two clock-source components:
• Always-on Si570 crystal oscillator
• Si5368 jitter-attenuating clock multiplier
Outputs from either source can be used to drive the transceiver reference clocks.
To start the SuperClock-2 module:
1. The SuperClock-2 module is configured using the Xilinx XC7Z010CLG225
Zynq-7000APSoC System Controller command line which can be accessed through a
serial communication terminal connection using the enhanced communication port of
the Silicon Labs USB to Dual UART Bridge
Silicon Labs USB-to-UART is available in Silicon Labs CP210x USB-to-UART Installation
Guide (UG1033)
Review the VCU1287 Evaluation Board User Guide (UG1120)
information about the System Controller.
X-Ref Target - Figure 1-9
2. Set the System Controller configuration DIP switches (SW13) to the OFF position
(Figure 1-10). This disables configuration of the FPGA at power reset.
X-Ref Target - Figure 1-10
VCU1287 IBERT Getting Started Guide
UG1203 (v2016.4) December 15. 2016
[Ref 3].
Figure 1-9: Silicon Labs Enhanced COM PORT
Figure 1-10: Configuration DIP Switch (SW13)
www.xilinx.com
Chapter 1: VCU1287 IBERT Getting Started Guide
(Figure 1-9). Additional information about the
[Ref 1]
ON
ENABLE
ADDR0
ADDR1
ADDR2
ADDR3
X15549-121416
for additional
X15548-121416
13
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