Xilinx Virtex UltraScale FPGA VCU1287 Getting Started Manual page 27

GTY Transceiver Clock Connections
Refer to Figure 1-2
reference clock inputs. Connect these cables to the SuperClock-2 module as follows:
• CLK0_P coax cable → SMA connector J7 (CLKOUT1_P) on the SuperClock-2 module
• CLK0_N coax cable → SMA connector J8 (CLKOUT1_N) on the SuperClock-2 module
Any one of the five differential outputs from the SuperClock-2 module can be used to source
Note:
the GTY reference clock. CLKOUT1_P and CLKOUT1_N are used here as an example.
GTY TX/RX Loopback Connections
Refer to Figure 1-2
receivers (RX0, RX1, RX2, and RX3) and the four transmitters (TX0, TX1, TX2,and TX3). Use
eight SMA female-to-female (F-F) adapters
cables as shown in
• TX0_P → SMA F-F Adapter → RX0_P
• TX0_N → SMA F-F Adapter → RX0_N
• TX1_P → SMA F-F Adapter → RX1_P
• TX1_N → SMA F-F Adapter → RX1_N
• TX2_P → SMA F-F Adapter → RX2_P
• TX2_N → SMA F-F Adapter → RX2_N
• TX3_P → SMA F-F Adapter → RX3_P
• TX3_N → SMA F-F Adapter → RX3_N
To ensure good connectivity, it is recommended that the adapters be secured with a wrench;
Note:
however, do not over tighten the SMAs.
VCU1287 IBERT Getting Started Guide
UG1203 (v2016.4) December 15. 2016
to identify the P and N coax cables that are connected to the CLK0
to identify the P and N coax cables that are connected to the four
Figure 1-7:
www.xilinx.com
Chapter 1: VCU1287 IBERT Getting Started Guide
(Figure 1-6) to connect the transmit and receive
27
Send Feedback