Interrupt Mask Register-3; Interrupt Status Register-1 - Motorola IXP-9120 Reference Manual

Table 29: Interrupt Mask Register-2
Bit
1
0

Interrupt Mask Register-3

Address: C700 000A
Type: R/W
Interrupts can be masked through the Interrupt mask registers. All interrupts are masked on
reset/power-on.
Table 30: Interrupt Mask Register-3
Bit Description
2 0: Voltage Monitor Interrupt is not masked
1: Voltage Monitor Interrupt is masked
Reset value: 1
1 0: Watchdog Timer Interrupt is not masked
1: Watchdog Timer Interrupt is masked
Reset value: 1
0 RFU
Reset value: 1
This bit must always be masked on the IXP/CPCI-9120.

Interrupt Status Register-1

Address: C700 000C
Type: Read Only
This register provides Interrupt status. When interrupted, the NPU can interrogate the three In-
terrupt status registers to determine the interrupt-source.
Description
0: RFU
1: RFU
0: RFU
1: RFU
Reset value: 1
Access
R/W
R/W
Access
R/W
R/W
RFU