Renesas R0E521000CPE00 User Manual page 62

R0E521000CPE00 User's Manual
3) Example Data Settings
Event setting for even-address word access (16-bit bus width)
STE.W A0,126h(A0=5423h)
16-bit bus width area (High-order and low-order data effective)
Event setting for even-address word access (8-bit bus width)
STE.W A0,400h(A0=5423h)
8-bit bus width area (Only Low-order data effective)
Event setting for odd-address word access
STE.W A0,401h(A0=AB79h)
8-bit bus width area (Only Low-order data effective)
Event setting for even-address byte access
STE.B R0L,[A1A0](R0L=E5h,A1=0000h,A0=0402h)
8-bit bus width area (Only Low-order data effective)
Event setting for odd-address byte access
STE.B R0L,[A1A0](R0L=E6h,A1=0000h,A0=0403h)
8-bit bus width area (Only Low-order data effective)
REJ10J0845-0600 Rev.6.00 Aug. 20, 2009
Page 60 of 92
3. Usage (How to Use the Emulator Debugger)
Setting a break event
A1
Address 1 :000126
Data 1 :5423
MASK :FFFF
Access :WRITE
Setting a break event
A1
Address 1 :000400
Data 1 :5423
MASK :00FF
Access :WRITE
Setting a break event (using 2 events)
A1
Address 1 :000401
Data 1 :0079
MASK :00FF
Access :WRITE
Set the combinatorial events to AND.
Setting a break event
A1
Address 1 :000402
Data 1 :00E5
MASK :00FF
Access :WRITE
Setting a break event
A1
Address 1 :000403
Data 1 :00E6
MASK :00FF
Access :WRITE
A2
Address 1 :000402
Data 1 :00AB
MASK :00FF
Access :WRITE