System Architecture - Analog Devices ADSP-CM403F EZ-KIT Lite Manual

System Architecture

System Architecture
This section describes the processor's configuration on the EZ-KIT Lite
(Figure 2-1).
30 MHz
Oscillator
3.3 Volts
JTAG
20 pin 0.1"
TRACE
20 pin 0.05"
Figure 2-1. EZ-KIT Lite Block Diagram
This EZ-KIT Lite is designed to demonstrate the ADSP-CM403F proces-
sor's capabilities. The ADSP-CM403F EZ-KIT Lite has a 30 MHz input
clock and runs at 240 MHZ internally.
2-2
DB9
Female
RJ11
RS-232 ADI
LEDs (3)
ADM3053
ADM3252E
UART0 CAN0
ADSP-CM403F
AFE
2 12-bit
2 16-bit ADCs
12 inputs each
DACs
Analog Connector
120 pin 0.5mm connector
AGND, 5V out, GND
ADSP-CM403F EZ-KIT Lite Evaluation System Manual
180 pin 0.5mm connector
PBs (2)
GPIO
UART2
32 Mbit Quad
SPI Flash
SPI0
TMR0:2
PWM0:2 SINC0 CNT0:1
PWM Connector
180 pin 0.5mm connector
5V in, 5V out, 3.3V out, GND
Asynchronous
connector
5V/3.3V out, GND
SMC0
SPI2
LCD
TWI0 display
2x20