Boot Mode Select Switch (SW1)
The rotary switch (
Table 2-5
shows the available boot mode settings. By default, the
ADSP-CM403F processor boots from the on-board burst flash memory.
Table 2-5. Boot Mode Select Switch (SW1)
SW1 Position
0
1
2
3
Reset Push Button (SW2)
The reset push button (
extender (
). The reset also is connected to the expansion interface via
U27
the
SYS_HWRST
GPIO Push Buttons (SW3-4)
The GPIO push buttons (
signals
PB_06/PWM2_AH/TM0_CLK/SMC0_D14
, respectively. The signals are connected by default.
SMC0_D15
ADSP-CM403F EZ-KIT Lite Evaluation System Manual
ADSP-CM403F EZ-KIT Lite Hardware Reference
) determines the boot mode of the processor.
SW1
Processor Boot Mode
No Boot – Idle
SPI master boot (internal SPI2). Default boot mode.
SPI slave boot (SPI0)
UART boot (UART0)
) resets the processor (
SW2
signal.
and
SW3
) and the GPIO
U1
) are connected to the processor's
SW4
and
PB_07/PWM2_AL/TM0_TMR0/
2-13
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