Functional Description; Introduction; Cpu; Memory And Input/Output Controller (Mioc) - HP 3000 Series Handbook

9
Functional Description
Introduction
This chapter describes the major hardware components of the system and the Access Port and
its associated commands.
CPU
Refer to Figure 9-1. The PCX-L Central Processing Unit (CPU) is a single-chip Precision
Architecture- Reduced Instruction Set Computer (PA-RISC) processor. The CPU conforms
to PA-RISC architecture, Edition 3. An additional feature is two-way superscalar operation.
It provides the ability to execute integer-integer and integer-floating point instruction bundles
in parallel. The CPU also contains an on-chip Floating Point Co-processor (FP), on- chip
Memory and Input/Output Controller (MIOC), on-chip Translation Lookaside Buffer (TLB),
and a first-level on-chip instruction cache.
Memory and Input/Output Controller (MIOC)
The MIOC handles the interface to memory via a private set of 72 data lines ( 64 data
+
8 ECC), and 24 address and control lines. The balance of the memory subsystem consists
of up to eight 72-bit ECC memory SIMMs, added in pairs of 8, 32, or 64 Megabytes. The
memory SIMMs are industry standard, except for the 64MB version, which is a double-high,
HP-proprietary version of the 32MB SIMM. All memory shipped with, and supported in
these system is made by HP. Note that memory must be added in like-pairs of 8/8 32/32, or
64/64MB.
Translation Lookaside Buffer (TLB)
The on-chip TLB contains space for 64 unified instruction/ data translation entries, eight
block translation entries, and an additional single instruction translation. The added single
instruction translation buffer contains the translation for the instruction page most recently
accessed. A hit on this buffer frees the balance of the TLB to perform a data translation
without any time penalty.
Cache
The CPU contains an on-chip one-kilobyte instruction cache in addition to the interface for an
off-chip instruction/data cache. The on-chip, level one I-cache serves to pre-fetch instructions
from the external. level two cache. The off-chip cache on the system board is made up of
standard SRAMs combined for a total of 64KB or 256KB of unified instruction/ data cache.
Functional Description 9-1