Access Status; Table 4.2 Bus Status Parameters - Renesas SH7040 Series Supplementary Information

4.2

Access Status

Table 4.2 lists the parameters for bus status (bus) that can be specified with HDI command line
interface or displayed as trace results.
Table 4.2 Bus Status Parameters
HDI Parameter
(Trace Display)
DMAC
(DMAC)
CACHE
(Cache)
DATA
(Data)
PROG
(Prog)
SLEEP_DMAC
(Sleep: DMAC)
Bus Status
On-chip DMAC
Cache fill
CPU data access
CPU instruction fetch
Sleep status
Description
Access by the MCU's DMAC
MCU internal cache fill cycle
Data access for instruction execution by
the CPU
Instruction fetch access by the CPU
DMAC cycle was generated in sleep
mode.
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