Page 1 The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7616 Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series SH7616 HD6417616 Rev. 2.00 Revision Date: Mar 09, 2006...
Page 2 (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp.
Page 3 Preface The SH7616 is a microprocessor that integrates peripheral functions necessary for system configuration with a 32-bit internal architecture SH2-DSP CPU as its core. The SH7616's on-chip peripheral functions include a cache memory, an interrupt controller, timers, an ethernet controller (EtherC), DSP, a serial communication interface with FIFO (SCIF),...
Page 4 User's Manuals on the SH7616: Manual Title ADE No. SH7616 Hardware Manual This manual SH-1/ SH-2/SH-DSP Software Manual REJ09B0171-0500O Users manuals for development tools: Manual Title ADE No. C/C++ Complier, Assembler, Optimized Linkage Editor User's Manual REJ10B0152-0101 Simulator Debugger Users Manual...
Page 5 Item Page Revision (See Manual for Details)  • Company name amended → Hitachi, Ltd. Renesas Technology Corp. • Amendments made due to change in package code → FP-208C PRQP0208KA-A 2.1.4 DSP Registers 37 Description added Figure 2.4 shows the DSP registers. The DSR register bit functions are shown in table 2.2.
Page 6 Item Page Revision (See Manual for Details) 10.2.8 Description amended Transmit/Receive Bit: . . . Status Copy Enable — — — . . . — — — — Register (TRSCER) Initial value: . . . R/W: . . . Bit: —...
Page 7 Item Page Revision (See Manual for Details) 10.3.1 Descriptor Figure amended List and Data Buffers Receive descriptor Receive Descriptor 31 30 29 28 Figure 10.3 Relationship between RFS 26 to RFS0 Receive Descriptor and Receive Buffer 16 15 Padding (4 bytes) Rev.
Page 8 Item Page Revision (See Manual for Details) 10.3.1 Descriptor Description amended List and Data Buffers Bit 27—Receive Frame Error (RFE): Indicates that one or other bit of Receive Descriptor 0 the receive frame status indicated by bits 26 to 0 is set. Whether or (TD0) not the multicast address frame receive information which is part of the frame status, is copied into this bit is specified by the...
Page 9 ↓ Receive Control Data Register Full (RCD) Possible * TDEI0 Transmit data register empty (TDRE)/ Transmit Control Data Register Empty (TCD) Appendix C Table amended Operating Table C.1 SH7616 Abbreviation Voltage Frequency Mark Code Package Product Lineup SH7616 3.3 V 62.5 MHz...
Page 10 Rev. 2.00 Mar 09, 2006 page x of xxvi...
Page 11: Table Of Contents
Contents Section 1 Overview ......................Features of SuperH Microcomputer with On-Chip Ethernet Controller ......Block Diagram ........................13 Pin Description........................14 1.3.1 Pin Arrangement ....................14 1.3.2 Pin Functions ....................... 15 1.3.3 Pin Multiplexing ....................21 Processing States....................... 27 Section 2 CPU ........................
Page 12 2.6.2 When executing a combination of double-precision multiplication or double-precision product-sum operation (CPU instruction) and DSP computing instruction ..................105 Section 3 Oscillator Circuits and Operating Modes ..........107 Overview........................... 107 On-Chip Clock Pulse Generator and Operating Modes ............ 107 3.2.1 Clock Pulse Generator ..................
Page 13 4.6.3 Instructions in Repeat Loops................140 Stack Status after Exception Handling................141 Usage Notes ........................142 4.8.1 Value of Stack Pointer (SP) ................. 142 4.8.2 Value of Vector Base Register (VBR) ..............142 4.8.3 Address Errors Caused by Stacking of Address Error Exception Handling ..142 4.8.4 Manual Reset during Register Access..............
Page 14 5.3.18 Vector Number Setting Register L (VCRL) ............175 5.3.19 Vector Number Setting Register M (VCRM) ............176 5.3.20 Vector Number Setting Register N (VCRN)............177 5.3.21 Vector Number Setting Register O (VCRO)............178 5.3.22 Vector Number Setting Register P (VCRP)............179 5.3.23 Vector Number Setting Register Q (VCRQ)............
Page 15 6.2.16 Break Data Mask Register D (BDMRD) ............. 223 6.2.17 Break Bus Cycle Register D (BBRD) ..............225 6.2.18 Break Execution Times Register D (BETRD) ............. 226 6.2.19 Break Control Register (BRCR) ................227 6.2.20 Branch Flag Registers (BRFR) ................233 6.2.21 Branch Source Registers (BRSR) ................
Page 16 7.4.1 Basic Timing......................282 7.4.2 Wait State Control....................287 CS Assertion Period Extension ................291 7.4.3 Synchronous DRAM Interface..................292 7.5.1 Synchronous DRAM Direct Connection ............. 292 7.5.2 Address Multiplexing................... 294 7.5.3 Burst Reads ......................296 7.5.4 Single Reads ......................301 7.5.5 Single Writes......................
Page 17 Section 8 Cache ........................357 Introduction........................357 8.1.1 Register Configuration..................358 Register Description......................358 8.2.1 Cache Control Register (CCR)................358 Address Space and the Cache.................... 360 Cache Operation........................ 361 8.4.1 Cache Reads......................361 8.4.2 Write Access ......................363 8.4.3 Cache-Through Access ..................366 8.4.4 The TAS Instruction.....................
Page 18 9.2.8 PHY Interface Status Register (PSR)..............389 9.2.9 Transmit Retry Over Counter Register (TROCR) ..........390 9.2.10 Single Collision Detect Counter Register (SCDCR)..........391 9.2.11 Delay Collision Detect Counter Register (CDCR) ..........392 9.2.12 Lost Carrier Counter Register (LCCR) ..............393 9.2.13 Carrier Not Detect Counter Register (CNDCR) ..........
Page 19 10.2.10 Transmit FIFO Threshold Register (TFTR)............439 10.2.11 FIFO Depth Register (FDR)................. 441 10.2.12 Receiver Control Register (RCR) ................ 442 10.2.13 E-DMAC Operation Control Register (EDOCR) ..........443 10.2.14 Receiving-Buffer Write Address Register (RBWAR) ......... 444 10.2.15 Receiving-Descriptor Fetch Address Register (RDFAR) ........445 10.2.16 Transmission-Buffer Read Address Register (TBRAR) ........
Page 20 11.4.1 Example of DMA Data Transfer Between SCIF and External Memory....516 11.5 Usage Notes ........................516 Section 12 16-Bit Free-Running Timer (FRT) ............519 12.1 Overview........................... 519 12.1.1 Features........................ 519 12.1.2 Block Diagram..................... 520 12.1.3 Pin Configuration....................521 12.1.4 Register Configuration..................521 12.2 Register Descriptions ......................
Page 21 13.1.4 Register Configuration..................545 13.2 Register Descriptions ......................545 13.2.1 Watchdog Timer Counter (WTCNT)..............545 13.2.2 Watchdog Timer Control/Status Register (WTCSR) ........... 546 13.2.3 Reset Control/Status Register (RSTCSR) ............547 13.2.4 Notes on Register Access..................549 13.3 Operation........................... 550 13.3.1 Operation in Watchdog Timer Mode ..............550 13.3.2 Operation in Interval Timer Mode ...............
Page 22 14.3.1 Overview......................591 14.3.2 Operation in Asynchronous Mode ............... 593 14.3.3 Multiprocessor Communication Function............605 14.3.4 Operation in Synchronous Mode ................. 613 14.3.5 Use of Transmit/Receive FIFO Buffers ............... 623 14.3.6 Operation in IrDA Mode..................626 14.4 SCIF Interrupt Sources and the DMAC ................630 14.5 Usage Notes ........................
Page 23 16.3.1 Input ........................675 16.3.2 Output ........................676 16.4 SIO Interrupt Sources and DMAC ..................679 Section 17 16-Bit Timer Pulse Unit (TPU) ..............681 17.1 Overview........................... 681 17.1.1 Features ........................ 681 17.1.2 Block Diagram ..................... 684 17.1.3 Pin Configuration....................685 17.1.4 Register Configuration..................
Page 24 Section 18 User Debug Interface (H-UDI) ..............751 18.1 Overview........................... 751 18.1.1 Features........................ 751 18.1.2 H-UDI Block Diagram..................752 18.1.3 Pin Configuration....................753 18.1.4 Register Configuration..................753 18.2 External Signals ........................ 754 18.2.1 Test Clock (TCK) ....................754 18.2.2 Test Mode Select (TMS)..................754 18.2.3 Test Data Input (TDI) ..................
Page 25 20.2.1 Register Configuration..................796 20.2.2 Port A Data Register (PADR) ................796 20.3 Port B ..........................797 20.3.1 Register Configuration..................797 20.3.2 Port B Data Register (PBDR) ................798 Section 21 Power-Down Modes ..................799 21.1 Overview........................... 799 21.1.1 Power-Down Modes .................... 799 21.1.2 Register ........................
Page 26 22.3.11 Ethernet Controller Timing.................. 875 22.3.12 STATS, BH, and BUSHiZ Signal Timing ............878 22.4 AC Characteristic Test Conditions..................880 Appendix A On-Chip Peripheral Module Registers ..........881 Addresses .......................... 881 Appendix B Pin States ....................... 900 Pin States in Reset, Power-Down State, and Bus-Released State ........900 Appendix C Product Lineup .....................
Page 27: Section 1 Overview
Features of SuperH Microcomputer with On-Chip Ethernet Controller The SH7616 is a CMOS single-chip microcontroller that integrates a high-speed CPU core using an original Renesas architecture with supporting functions required for an Ethernet system. The CPU has a RISC (Reduced Instruction Set Computer) type instruction set. The CPU basically operates at a rate of one instruction per cycle, offering a great improvement in instruction execution speed.
Page 28 Section 1 Overview Table 1.1 Features Item Specifications • Original Renesas architecture • 32-bit internal architecture • General register machine  Sixteen 32-bit general registers  Six 32-bit control registers (including 3 added for DSP use)  Ten 32-bit system registers •...
Page 29 Section 1 Overview Item Specifications • DSP engine  Multiplier  Arithmetic logic unit (ALU)  Shifter  DSP registers • Multiplier  16 bits × 16 bits → 32 bits  Single-cycle multiplier • DSP registers  Two 40-bit data registers ...
Page 30 Section 1 Overview Item Specifications Cache • Mixed instruction/data type cache • Maximum of 4 kbytes • 4-way set-associative type • 16-byte line length • 64 cache tag entries • 16-byte write-back buffer • Selection of write-through or write-back mode for data writes •...
Page 31 Section 1 Overview Item Specifications User break • Interrupt generation based on independent or sequential conditions for controller (UBC), channels A, B, C, D 4 channels  Three sequential setting patterns: A → B → C → D, B → C → D, (A, B, C, D) C →...
Page 32 Section 1 Overview Item Specifications Bus state controller • Address space divided into five areas (CS0 to CS4, max. linear 32 Mbytes (BSC) each)  Memory types such as DRAM, synchronous DRAM, burst ROM, can be specified for each area ...
Page 33 Section 1 Overview Item Specifications Direct memory • 4-Gbyte address space, maximum 16M (16,777,216) transfers access controller • Selection of 8-bit, 16-bit, 32-bit, or 16-byte transfer data length (DMAC), • Parallel execution of CPU instruction processing and DMA operation 2 channels possible in case of cache hit •...
Page 34 Section 1 Overview Item Specifications Ethernet controller • MAC (Media Access Control) functions (EtherC)  Data frame assembly/disassembly (IEEE802.3-compliant frames)  CSMA/CD link management (collision avoidance, processing in case of collision)  CRC processing  Supports full-duplex transmission/reception  Transmitting and receiving short and long packets •...
Page 35 Section 1 Overview Item Specifications Serial communi- • Four interrupt sources cation interface  Transmit FIFO data empty with FIFO (SCIF),  Break 2 channels  Receive FIFO data full  Receive error Built-in modem control functions (RTS, CTS) • •...
Page 36 Section 1 Overview Item Specifications • Conforms to IEEE1149.1 standard User debug  Five test signals (TCK, TDI, TDO, TMS, TRST) interface (H-UDI)  TAP controller  Instruction register  Data register  Bypass register • Test mode that conforms to the IEEE1149.1 standard ...
Page 37 Section 1 Overview Item Specifications 16-bit free-running • Choice of four counter input clocks timer (FRT),  Three internal clocks (Pφ/8, Pφ/32, Pφ/128) 1 channel  External clock (enabling external event counting) • Two independent comparators (allowing generation of two waveform outputs) •...
Page 38 Section 1 Overview Item Specifications System controller • Selection of seven operating mode settings, three power-down modes (SYSC) • Operating modes  Control the method of clock generation (PLL ON/OFF) and clock division ratio • Power-down mode  Sleep mode: CPU functions halted ...
Page 39: Block Diagram
Bus state controller Direct Clock pulse memory access generator controller Ethernet System controller controller Ethernet controller direct memory access I/O ports controller External bus interface Figure 1.1 Block Diagram of SH7616 Rev. 2.00 Mar 09, 2006 page 13 of 906 REJ09B0292-0200...
Page 40: Pin Description
Note: * When doing debugging using the E10A emulator, this pin is used for mode switching. It should be connected to Vss when using the E10A emulator and connected to Vcc when using a normal user system. Figure 1.2 SH7616 Pin Arrangement (PLQP0208KA-A) Rev. 2.00 Mar 09, 2006 page 14 of 906...
Page 41: Pin Functions
Section 1 Overview 1.3.2 Pin Functions Table 1.2 Pin Functions Type Symbol Name Function Power Input Power For connection to the power supply. Connect all V pins to the system power supply. The chip will not operate if there are any open pins Input Ground For connection to ground.
Page 42 Section 1 Overview Type Symbol Name Function When RES = 0 and NMI = 1, the chip System Input Reset control enters the power-on reset state. When RES = 0 and NMI = 0, the chip enters the manual reset state WDTOVF Output Watchdog...
Page 43 Section 1 Overview Type Symbol Name Function Bus control Output Column Synchronous DRAM CAS signal address strobe Output Output enable EDO DRAM output enable signal Used in access in RAS down mode DQMUU/ Output Highest byte SRAM/synchronous DRAM highest byte access select signal DQMUL/...
Page 44 Section 1 Overview Type Symbol Name Function Bus control A24–A0 Output Address bus Address output D31–D0 Data bus Data input/output H-UDI Input Test clock Test clock input Input Test mode Test mode select input signal select Input Test data input Serial data input Output Test data output...
Page 45 Section 1 Overview Type Symbol Name Function Ethernet LNKSTA Input Link status Link status input from PHY controller EXOUT Output General-purpose General-purpose external output pin (EtherC) external output Output Wake on LAN Signal indicating detection of a Magic Packet CAMSEN Input CAM sense CAM sense signal...
Page 46 Section 1 Overview Type Symbol Name Function Timer pulse TIOCA2 TPU input Channel 2 input capture input/output unit (TPU) TIOCB2 capture/output compare output/PWM output pins compare (channel 2) 16-bit FTCI Input Counter clock FRC counter clock input pin free-running input timer (FRT) FTOA Output...
Page 47: Pin Multiplexing
Section 1 Overview Type Symbol Name Function PA0–PA13 * I/O I/O ports General port General input/output port pins Input or output can be specified bit by bit PB0–PB15 General port General input/output port pins Input or output can be specified bit by bit Note: * PA3 cannot be used;...
Page 48 Section 1 Overview Function 1 Function 2 Function 3 Function 4 Type Bus control BRLS WAIT CAS/OE DQMUU/WE3 DQMUL/WE2 DQMLU/WE1 DQMLL/WE0 CAS3 CAS2 CAS1 CAS0 REFOUT RD/WR BUSHiZ 25 pins Rev. 2.00 Mar 09, 2006 page 22 of 906 REJ09B0292-0200...
Page 49 Section 1 Overview Function 1 Function 2 Function 3 Function 4 Type Address bus 25 pins Rev. 2.00 Mar 09, 2006 page 23 of 906 REJ09B0292-0200...
Page 50 Section 1 Overview Function 1 Function 2 Function 3 Function 4 Type Data bus 32 pins Rev. 2.00 Mar 09, 2006 page 24 of 906 REJ09B0292-0200...
Page 51 Section 1 Overview Function 1 Function 2 Function 3 Function 4 Type H-UDI TRST ASEMODE * 6 pins TX-CLK EtherC RX-CLK TX-EN 5 V I/O compatibility ETXD3 ETXD2 ETXD1 ETXD0 TX-ER RX-DV ERXD3 ERXD2 ERXD1 ERXD0 RX-ER MDIO 18 pins DACK1 DMAC DACK0...
Page 52 Section 1 Overview Function 1 Function 2 Function 3 Function 4 [00] * [01] * [10] * [11] * Type PB15 SCK1 Port B PB14 RXD1 SCIF, SIO, TPU PB13 TXD1 PB12 SRCK2 STATS1 5 V I/O compatibility PB11 SRS2 STATS0 PB10 SRXD2...
Page 53: Processing States
Section 1 Overview When used for general input/output, attention must be paid to the polarity of this pin. Processing States State Transitions: The CPU has five processing states: the reset state, exception handling state, bus-released state, program execution state, and power-down state. Figure 1.3 shows the state transitions.
Page 54 Section 1 Overview • Reset State In this state, the CPU is reset. The reset state is entered when the RES pin goes low. The power-on reset state is entered if the NMI pin is high, and the manual reset state is entered if the NMI pin is low.
Page 55 Section 1 Overview • Standby Mode A transition to standby mode is made if the SLEEP instruction is executed while SBY is set to 1 in SBYCR1. In standby mode the CPU, the on-chip modules, and the oscillator all stop. When entering standby mode, the DMAC’s DMA master enable bit should be cleared to 0.
Page 56 Section 1 Overview Table 1.4 Power-Down State State On-Chip On-chip Cache or Entering Supporting On-Chip Exiting Mode Conditions Clock Modules Registers Conditions 1. Interrupt Sleep Executing Operating Halted Operating Held Held mode SLEEP 2. DMA address instruction error while SBY bit 3.
Page 57: Section 2 Cpu
Section 2 CPU Section 2 CPU Register Configuration The register set consists of sixteen 32-bit general registers, six 32-bit control registers and ten 32- bit system registers. This chip is upwardly compatible with the SH-1, SH-2 on the object code level. For this reason, several registers have been added to the previous SuperH microcontroller registers.
Page 58 Section 2 CPU R2, [As] R3, [As] R4, [As, Ax] R5, [As, Ax] R6, [Ay] R7, [Ay] R8, [Ix, Is] R9, [Iy] R15, SP Notes: R0 also functions as an index register in the indirect indexed register addressing mode and indirect indexed GBR addressing mode. In some instructions, only the R0 functions as a source register or destination register.
Page 59: Control Registers
Section 2 CPU The name Ix is an alias for R8. The other aliases are assigned as follows: Ax0: .REG (R4) Ax1: .REG (R5) .REG (R8) Ay0: .REG (R6) Ay1: .REG (R7) .REG (R9) defined when an alias is required for single data transfer As0: .REG (R4) defined when an alias is required for single data transfer...
Page 60 Section 2 CPU Figure 2.2 shows the control registers. Table 2.1 indicates the SR register bits. Status register (SR) 31 28 27 16 15 12 11 10 9 8 7 2 1 0 0000 0000 I3 I2 I1 I0 RF1 RF0 Repeat start register (RS) Repeat end register (RE) Global base register (GBR)
Page 61 Section 2 CPU Table 2.1 SR Register Bits Name (Abbreviation) Function 27–16 Repeat counter (RC) Designate the repeat count (2–4095) for repeat (loop) control Y pointer usage modulo 1: modulo addressing mode becomes valid for Y addressing designation memory address pointer, Ay (R6, R7) (DMY) X pointer usage modulo 1: modulo addressing mode becomes valid for X...
Page 62: System Registers
Section 2 CPU There are dedicated load/store instructions for accessing the RS, RE and MOD registers. For example, the RS register is accessed as follows. Rm,RS; Rm→RS LDC.L @Rm+,RS; (Rm)→RS,Rm+4→Rm RS,Rn; RS→Rn STC.L RS,@-Rn; Rn-4→Rn,RS→(Rn) The following instructions set addresses in the RS, RE registers for zero overhead repeat control: LDRS @(disp,PC);...
Page 63: Dsp Registers
Section 2 CPU In addition, among the DSP unit usage registers (DSP registers) described in 2.1.4 DSP Registers, the DSP status register (DSR) and the five registers A0, X0, X1, Y0 and Y1 of the eight data registers are treated as system registers. Among these, the A0 is a 40-bit register, but when data is output from the A0 register, the guard bit section (A0G) is disregarded;...
Page 64 Section 2 CPU 32 31 DSP data registers 3 2 1 0 GT Z N V CS[2:0] DC DSP status register (DSR) Figure 2.4 DSP Register Configuration Rev. 2.00 Mar 09, 2006 page 38 of 906 REJ09B0292-0200...
Page 65 Section 2 CPU Table 2.2 DSR Register Bits Name (Abbreviation) Function 31–8 Reserved bits 0: Always read out; always use 0 as a write value Signed greater than bit Indicates that the operation result is positive (GT) (excepting 0), or that operand 1 is greater than operand 2 1: Operation result is positive, or operand 1 is greater Zero bit (Z)
Page 66: Notes On Guard Bits And Overflow Treatment
Section 2 CPU 2.1.5 Notes on Guard Bits and Overflow Treatment DSP unit data operations are fundamentally performed as 32-bit, but these operations are always executed with a 40-bit length including the 8-bit guard section. When the guard bit section does not match the value of the 32-bit section MSB, the operation result is treated as an overflow.
Page 67: Data Formats
Section 2 CPU Data Formats 2.2.1 Data Format in Registers Register operand data size is always longword (32 bits). When loading data from memory into a register, if the memory operand is a byte (8 bits) or a word (16 bits), it is sign-extended into a longword, then loaded into the register.
Page 68: Immediate Data Format
Section 2 CPU 2.2.3 Immediate Data Format Byte immediate data is placed in an instruction code. With the MOV, ADD, and CMP/EQ instructions, immediate data is sign-extended and operated in registers as longword data. Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and handled as longword data.
Page 69 Section 2 CPU DSP fixed decimal point data –31 With guard bits –2 to +2 – 2 –31 No guard bits –1 to +1 – 2 16 15 –15 Multiplication input –1 to +1 – 2 DSP integer data With guard bits –2 to +2 –1...
Page 70: Dsp Type Instructions And Data Formats
Section 2 CPU 2.2.5 DSP Type Instructions and Data Formats The DSP data format and valid data length are determined by DSP type instructions and DSP registers. There are three types of instructions that access DSP data registers, DSP data processing, X, Y data transfer processing, and single data transfer processing instructions.
Page 71 Section 2 CPU treated as independent registers during single data transfers. The load/store data length for the A0G, A1G registers is 8 bits. If DSP registers are used as source registers in word mode, when data is stored from any registers other than A0G, A1G, the data in the upper word of the register is transferred.
Page 72 Section 2 CPU Table 2.4 Source Register Data Formats for DSP Instructions Register Bits Guard Bits Register Instruction 39–32 31–16 15–0 A0, A1 Fixed decimal, 40-bit data operation PDMSB, PSHA Integer 24-bit data — Logic, PSHL, — 16-bit data PMULS Data MOVX.W, transfer...
Page 73 Section 2 CPU Table 2.5 Destination Register Data Formats for DSP Instructions Register Bits Guard Bits Register Instruction 39–32 31–16 15–0 A0, A1 Fixed (Sign extend) 40-bit result operation decimal, PSHA, PMULS Integer, 24-bit result Clear to 0 PDMSB Logic, PSHL Clear to 0 16-bit result Data transfer...
Page 74: Cpu Core Instruction Features
Section 2 CPU 32 bits 16 bits 16 bits [7:0] 32 bits 8 bits 16 bits MOVS.W, MOVS.L MOVX.W, MOVY.W MOVS.W, MOVS.L Figure 2.8 DSP Register-Bus Relationship during Data Transfers CPU Core Instruction Features The CPU core instructions are RISC type. The characteristics are as follows. 16-Bit Fixed Length: All instructions are 16 bits long, increasing program code efficiency.
Page 75 Section 2 CPU Table 2.6 Sign Extension of Word Data SH7616 CPU Description Example of Conventional CPU MOV.W @(disp,PC),R1 Data is sign-extended to 32 ADD.W #H'1234,R0 bits, and R1 becomes R1,R0 H'00001234. It is next operated ..upon by an ADD instruction .DATA.W H'1234...
Page 76 The number of instructions modifying the T bit is kept to a minimum to improve the processing speed. Table 2.8 T Bit SH7616 CPU Description Example of Conventional CPU T bit is set when R0 ≥ R1.
Page 77 Loading the immediate data when the instruction is executed transfers that value to the register and the data is accessed in the indirect register addressing mode. Table 2.10 Absolute Address Accessing Classification SH7616 CPU Example of Conventional CPU Absolute address MOV.L @(disp,PC),R1 MOV.B @H'12345678,R0...
Page 78: Instruction Formats
Section 2 CPU Instruction Formats 2.4.1 CPU Instruction Addressing Modes The addressing modes and effective address calculation for instructions executed by the CPU core are listed in table 2.12. Table 2.12 CPU Instruction Addressing Modes and Effective Addresses Addressing Instruction Mode Format Effective Addresses Calculation...
Page 79 Section 2 CPU Addressing Instruction Mode Format Effective Addresses Calculation Equation Indirect register @(disp:4, The effective address is Rn plus a 4-bit Byte: Rn + disp addressing displacement (disp). The value of disp is zero- Word: Rn + disp × with extended, and remains the same for a byte displacement...
Page 80 Section 2 CPU Addressing Instruction Mode Format Effective Addresses Calculation Equation Indirect @(R0, The effective address is the GBR value plus the R0 GBR + R0 indexed GBR GBR) addressing GBR + R0 PC relative @(disp:8, The effective address is the PC value plus an Word: PC + disp ×...
Page 81 Section 2 CPU PC + disp × 2 PC relative disp:8 The effective address is the PC value sign-extended addressing with an 8-bit displacement (disp), doubled, and added to the PC value PC + disp × 2 disp (sign-extended) × PC + disp ×...
Page 82: Dsp Data Addressing
Section 2 CPU 2.4.2 DSP Data Addressing There are two different kinds of memory accesses with DSP instructions. One type is with the X, Y data transfer instructions (MOVX.W, MOVY.W), and the other is with the single data transfer instructions (MOVS.W, MOVS.L). The data addressing differs between these two types of instructions.
Page 83 Section 2 CPU 3. Increment address registers: The Ax, Ay registers are address pointers. The value +2 is added to each of them after the data transfer (post-update). Each of the address pointers has an index register. The R8 register becomes the index register (Ix) of the X memory address register (Ax), and the R9 register becomes the index register (Iy) of the Y memory address register (Ay).
Page 84 Section 2 CPU Single Data Addressing: Among the DSP instructions, the single data transfer instructions (MOVS.W and MOVS.L) are used to either load data into DSP registers or to store it from them. With these instructions, the registers R2 to R5 are used as address registers (As) for the single data transfers.
Page 85 Section 2 CPU Modulo Addressing: The chip has a modulo addressing mode, just as other DSPs do. Address registers are updated in the same manner as with other modes. When the address pointer value becomes the same as a previously established modulo end address, the address pointer becomes the modulo start address.
Page 86 Section 2 CPU Instruction (MOVX/MOVY) R4[Ax] R6[Ay] R8[Ix] R5[Ax] R7[Ay] R9[Iy] CONT Figure 2.11 Modulo Addressing An example of modulo addressing is indicated below: MS=H'E008; ME=H'E00C; R4=H'1000E008; DMX=1; DMY=0; (sets modulo addressing for address register Ax (R4, R5)) The R4 register changes as follows due to the above settings. R4: H'1000E008 Inc.
Page 87 Section 2 CPU DSP Addressing Operation: The DSP addressing operation in the item stage (EX) of the pipeline, including modulo addressing, is indicated below. if ( Operation is MOVX.W MOVY.W ) { ABx=Ax; ABy=Ay; /* memory access cycle uses ABx and ABy. The addresses to be used have not been updated */ /* Ax is one of R4,5 */ if ( DMX==0 || DMX==1 &&...
Page 88: Instruction Formats For Cpu Instructions
Section 2 CPU if operation is not-update function modulo ( AddrReg, Index ) { if ( AdrReg[15:0]==ME ) AdrReg[15:0]=MS; else AdrReg=AdrReg+Index; return AddrReg; 2.4.3 Instruction Formats for CPU Instructions The instruction format of instructions executed by the CPU core and the meanings of the source and destination operands are indicated below.
Page 89 Section 2 CPU Table 2.14 Instruction Formats for CPU Instructions Destination Instruction Formats Source Operand Operand Example 0 format — — xxxx xxxx xxxx xxxx n format — nnnn: Direct MOVT Rn register xxxx nnnn xxxx xxxx Control register or nnnn: Direct STS MACH,Rn system register...
Page 90 Section 2 CPU Destination Instruction Formats Source Operand Operand Example nm format mmmm: Direct nnnn: Direct Rm,Rn register register mmmm: Direct nnnn: Indirect MOV.L Rm,@Rn register register xxxx nnnn xxxx mmmm mmmm: Indirect post- MACH, MACL MAC.W increment register @Rm+,@Rn+ (multiply/ accumulate) nnnn: Indirect post-...
Page 91 Section 2 CPU Destination Instruction Formats Source Operand Operand Example d format dddddddd: Indirect R0 (Direct register) MOV.L GBR with @(disp,GBR),R0 displacement xxxx xxxx dddd dddd R0(Direct register) dddddddd: Indirect MOV.L GBR with R0,@(disp,GBR) displacement dddddddd: PC R0 (Direct register) MOVA relative with @(disp,PC),R0 displacement...
Page 92: Instruction Formats For Dsp Instructions
Section 2 CPU 2.4.4 Instruction Formats for DSP Instructions New instructions have been added for digital signal processing. The new instructions are divided into the two following types. 1. Memory and DSP register double, single data transfer instructions (16 bit length) 2.
Page 93 Section 2 CPU Table 2.15 Instruction Formats for Double Data Transfers Category Mnemonic X memory NOPX data transfers MOVX.W @Ax,Dx MOVX.W @Ax+,Dx MOVX.W @Ax+Ix,Dx MOVX.W Da,@Ax MOVX.W Da,@Ax+ MOVX.W Da,@Ax+Ix Y memory NOPY data transfers MOVY.W @Ay,Dy MOVY.W @Ay+,Dy MOVY.W @Ay+Iy,Dy MOVY.W Da,@Ay...
Page 94 Section 2 CPU Table 2.16 Instruction Formats for Single Data Transfers Category Mnemonic Single data MOVS.W @–As,Ds transfer 0: R4 MOVS.W @As,Ds 1: R5 MOVS.W @As+,Ds 2: R2 MOVS.W @As+Is,Ds 3: R3 MOVS.W Ds,@-As MOVS.W Ds,@As MOVS.W Ds,@As+ MOVS.W Ds,@As+Is MOVS.L @–As,Ds MOVS.L...
Page 95 Section 2 CPU Parallel Processing Instructions: The parallel processing instructions allow for more efficient execution of digital signal processing using the DSP unit. They are 32 bit length, allowing simultaneously in parallel four processes, ALU operations, multiplications or 2 data transfers. The parallel processing instructions are divided into A fields and B fields.
Page 96 Section 2 CPU Category Mnemonic 15–0 X memory B field NOPX data MOVX.W @Ax,Dx transfers MOVX.W @Ax+,Dx MOVX.W @Ax+Ix,Dx MOVX.W Da,@Ax MOVX.W Da,@Ax+ MOVX.W Da,@Ax+Ix Y memory NOPY data MOVY.W @Ay,Dy transfers MOVY.W @Ay+,Dy MOVY.W @Ay+Iy,Dy MOVY.W Da,@Ay MOVY.W Da,@Ay+ MOVY.W Da,@Ay+Iy Ax: 0 = R4, 1 = R5 Ay: 0 = R6, 1 = R7 Dx: 0 = X0, 1 = X1 Dy: 0 = Y0, 1 = Y1 Da: 0 = A0, 1 = A1...
Page 97 Section 2 CPU Table 2.18 B Field ALU Operation Instructions, Multiplication Instructions Category Mnemonic 31–27 25–16 14 13 12 10 9 8 7 6 5 4 3 2 1 0 –16 ≤ lmm ≤ +16 A field 0 0 0 PSHL #lmm, Dz Imm.
Page 98: Instruction Set
Section 2 CPU Category Mnemonic 31–27 25–16 14 13 12 10 9 8 7 6 5 4 3 2 1 0 if cc (if cc) PSHL Sx, Sy, Dz A field Conditional (if cc) PSHA Sx, Sy, Dz three (if cc) PSUB Sx, Sy, Dz operand instructions (if cc) PADD Sx, Sy, Dz...
Page 99: Cpu Instruction Set
Section 2 CPU 2.5.1 CPU Instruction Set Table 2.19 lists the CPU instructions by classification. Table 2.19 Classification of CPU Instructions Operation No. of Classification Types Code Function Instructions Data transfer Data transfer, immediate data transfer, peripheral module data transfer, structure data transfer MOVA Effective address transfer MOVT...
Page 100 Section 2 CPU Operation No. of Classification Types Code Function Instructions Logic Logical AND operations Bit inversion Logical OR Memory test and bit set Logical AND and T bit set Exclusive OR Shift ROTCL One-bit left rotation with T bit ROTCR One-bit right rotation with T bit ROTL...
Page 101 Section 2 CPU Operation No. of Classification Types Code Function Instructions System CLRMAC MAC register clear control CLRT T bit clear Load to control register LDRE Load to repeat end register LDRS Load to repeat start register Load to system register No operation Return from exception processing SETRC...
Page 102 Section 2 CPU The instruction codes, operation, and execution states of the CPU instructions are listed by classification with the formats listed in below. Execution Instruction Instruction Code Operation Cycles T Bit Indicated in MSB ↔ Indicated by mnemonic Indicates summary of Value when Value of T bit LSB order...
Page 103 Section 2 CPU Table 2.20 Data Transfer Instructions Instruction Instruction Code Operation Cycles T Bit 1110nnnniiiiiiii imm → Sign extension → — #imm,Rn 1001nnnndddddddd (disp × 2 + PC) → Sign — MOV.W @(disp,PC),Rn extension → Rn 1101nnnndddddddd (disp × 4 + PC) → Rn —...
Page 104 Section 2 CPU Instruction Instruction Code Operation Cycles T Bit Rm → (R0 + Rn) — MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110 (R0 + Rm) → Sign — MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100 extension → Rn (R0 + Rm) → Sign — MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101 extension →...
Page 105 Section 2 CPU Table 2.21 Arithmetic Instructions Instruction Instruction Code Operation Cycles T Bit Rn + Rm → Rn — Rm,Rn 0011nnnnmmmm1100 Rn + imm → Rn — #imm,Rn 0111nnnniiiiiiii Rn + Rm + T → Rn, Carry ADDC Rm,Rn 0011nnnnmmmm1110 Carry →...
Page 106 Section 2 CPU Instruction Instruction Code Operation Cycles T Bit 0011nnnnmmmm1101 Signed operation of 2 to 4 — DMULS.L Rm,Rn Rn × Rm → MACH, MACL 32 × 32 → 64 bits 0011nnnnmmmm0101 Unsigned operation of 2 to 4 — DMULU.L Rm,Rn Rn ×...
Page 107 Section 2 CPU Instruction Instruction Code Operation Cycles T Bit Rn–Rm → Rn — Rm,Rn 0011nnnnmmmm1000 Rn–Rm–T → Rn, Borrow SUBC Rm,Rn 0011nnnnmmmm1010 Borrow → T Rn–Rm → Rn, Underflow SUBV Rm,Rn 0011nnnnmmmm1011 Underflow → T Note: * The normal number of execution cycles. The number in parentheses is the number of execution cycles in the case of contention with preceding or following instructions.
Page 108 Section 2 CPU Table 2.23 Shift Instructions Instruction Instruction Code Operation Cycles T Bit T ← Rn ← MSB ROTL 0100nnnn00000100 LSB → Rn → T ROTR 0100nnnn00000101 T ← Rn ← T ROTCL Rn 0100nnnn00100100 T → Rn → T ROTCR Rn 0100nnnn00100101 T ←...
Page 109 Section 2 CPU Table 2.24 Branch Instructions Instruction Instruction Code Operation Cycles T Bit If T = 0, disp × 2 + PC → PC, — label 10001011dddddddd if T = 1, nop Delayed branch, if T = 0, disp × 2 —...
Page 110 Section 2 CPU Table 2.25 System Control Instructions Instruction Instruction Code Operation Cycles T Bit 0 → MACH, MACL — CLRMAC 0000000000101000 0 → T CLRT 0000000000001000 Rm → SR Rm,SR 0100mmmm00001110 Rm → GBR — Rm,GBR 0100mmmm00011110 Rm → VBR —...
Page 111 Section 2 CPU Instruction Instruction Code Operation Cycles T Bit (Rm) → DSR, Rm + 4 → Rm — LDS.L @Rm+,DSR 0100mmmm01100110 (Rm) → A0, Rm + 4 → Rm — LDS.L @Rm+,A0 0100mmmm01110110 (Rm) → X0, Rm + 4 → Rm —...
Page 112 Section 2 CPU Instruction Instruction Code Operation Cycles T Bit MACH → Rn — MACH,Rn 0000nnnn00001010 MACL → Rn — MACL,Rn 0000nnnn00011010 PR → Rn — PR,Rn 0000nnnn00101010 DSR → Rn — DSR,Rn 0000nnnn01101010 A0 → Rn — A0,Rn 0000nnnn01111010 X0 →...
Page 113 Section 2 CPU Precautions Concerning the Number of Instruction Execution Cycles: The execution cycles listed in the tables are minimum values. In practice, the number of execution cycles increases under such conditions as 1) when the instruction fetch is in contention with a data access, 2) when the destination register of a load instruction (memory →...
Page 114 Section 2 CPU Table 2.26 Added CPU Instructions Instruction Code Operation Cycles T Bit Rm→MOD — Rm,MOD 0100mmmm01011110 Rm→RE — Rm,RE 0100mmmm01111110 Rm→RS — Rm,RS 0100mmmm01101110 (Rm)→MOD,Rm+4→Rm — LDC.L @Rm+,MOD 0100mmmm01010111 (Rm)→RE,Rm+4→Rm — LDC.L @Rm+,RE 0100mmmm01110111 (Rm)→RS,Rm+4→Rm — LDC.L @Rm+,RS 0100mmmm01100111 MOD→Rn —...
Page 115: Dsp Data Transfer Instruction Set
Section 2 CPU Instruction Code Operation Cycles T Bit Rn–4→Rn,X1→(Rn) — STS.L X1,@-Rn 0100nnnn10010010 Y0→Rn — Y0,Rn 0000nnnn10101010 Rn–4→Rn,Y0→(Rn) — STS.L Y0,@-Rn 0100nnnn10100010 Y1→Rn — Y1,Rn 0000nnnn10111010 Rn–4→Rn,Y1→(Rn) — STS.L Y1,@-Rn 0100nnnn10110010 Rm[11:0]→RC (SR[27:16]) 1 — SETRC 0100mmmm00010100 imm→RC(SR[23:16]), — SETRC #imm 10000010iiiiiiii...
Page 116 Section 2 CPU pointer is used to access X memory; the Ay pointer is used to access Y memory. Double data transfers can only access X, Y memory. Single data transfers can be accessed from any area. Single data transfers use the Ax pointer and two other pointers as an As pointer.
Page 117 Section 2 CPU Table 2.30 Single Data Transfer Instructions Instruction Operation Code Cycles DC Bit As–2→As,(As)→MSW of — MOVS.W 111101AADDDD0000 Ds,0→LSW of Ds @-As,Ds (As)→MSW of Ds,0→LSW of — MOVS.W @As,Ds 111101AADDDD0100 (As)→MSW of Ds,0→LSW of — MOVS.W 111101AADDDD1000 Ds, As+2→As @As+,Ds (As)→MSW of Ds,0→LSW of —...
Page 118 Section 2 CPU Table 2.31 shows the correspondence between the DSP data transfer operands and registers. CPU core registers are used as pointer addresses indicating memory addresses. Table 2.31 Correspondence between DSP Data Transfer Operands and Registers SH (CPU Core) Registers Oper- (Ax0) (Ax1)
Page 119: Dsp Operation Instruction Set
Section 2 CPU 2.5.3 DSP Operation Instruction Set DSP operation instructions are digital signal processing instructions processed by the DSP unit. These instructions use 32-bit instruction codes, and multiple instructions are executed in parallel. The instruction codes are divided into an A field and a B field; parallel data transfer instructions are designated in the A field, and single or double data operation instructions are designated in the B field.
Page 120 Section 2 CPU Table 2.33 Correspondence between DSP Instruction Operands and Registers ALU and BPU Instructions Multiplication Instructions Register — — — — — — — — — — — — — — — — — — — — — —...
Page 121 Section 2 CPU Table 2.34 Classification of DSP Instructions Instruction Operation No. of In- Classification Types Code Function structions ALU arith- ALU fixed decimal PABS Absolute value metic point operation operation instructions operation PADD Addition instruc- PADD Addition and signed tions PMULS multiplication...
Page 122: Various Operation Instructions
Section 2 CPU 2.5.4 Various Operation Instructions ALU Arithmetic Operation Instructions: Tables 2.35–2.44 list various operation instructions. Table 2.35 ALU Fixed Point Operation Instructions Instruction Operation Code Cycles DC Bit If Sx≥0,Sx→Dz Update PABS Sx,Dz 111110********** If Sx<0,0– Sx→Dz 10001000xx00zzzz If Sy≥0,Sy→Dz Update PABS Sy,Dz...
Page 123 Section 2 CPU Instruction Operation Code Cycles DC Bit if DC=1,Sy→Dz if 0,nop — DCT PCOPY 111110********** Sy,Dz 1111101000yyzzzz if DC=0,Sx→Dz if 1,nop — DCF PCOPY 111110********** Sx,Dz 11011011xx00zzzz if DC=0,Sy→Dz if 1,nop — DCF PCOPY 111110********** Sy,Dz 1111101100yyzzzz 0–Sx→Dz Update PNEG Sx,Dz 111110**********...
Page 124 Section 2 CPU Table 2.36 ALU Integer Operation Instructions Instruction Operation Code Cycles DC Bit MSW of Sx – 1 → MSW of Update PDEC Sx,Dz 111110********** Dz, clear LSW of Dz 10001001xx00zzzz MSW of Sy – 1 → MSW of Update PDEC Sy,Dz 111110**********...
Page 125 Section 2 CPU Table 2.37 MSB Detection Instructions Instruction Operation Code Cycles DC Bit Sx data MSB position → Update PDMSB Sx,Dz 111110********** MSW of Dz, clear LSW of 10011101xx00zzzz Sy data MSB position → Update PDMSB Sy,Dz 111110********** MSW of Dz, clear LSW of 1011110100yyzzzz If DC=1, Sx data MSB —...
Page 126 Section 2 CPU Table 2.39 ALU Logical Operation Instructions Instruction Operation Code Cycles DC Bit Sx & Sy → Dz, clear LSW Update PAND Sx,Sy,Dz 111110********** of Dz 10010101xxyyzzzz If DC=1, Sx & Sy → Dz, — DCT PAND 111110********** clear LSW of Dz;...
Page 127 Section 2 CPU Table 2.41 Arithmetic Shift Operation Instructions Instruction Operation Code Cycles DC Bit if Sy≥0,Sx<<Sy→Dz Update PSHA Sx,Sy,Dz 111110********** if Sy<0,Sx>>Sy→Dz 10010001xxyyzzzz if DC=1 & — DCT PSHA 111110********** Sy≥0,Sx<<Sy→Dz Sx,Sy,Dz 10010010xxyyzzzz if DC=1 & Sy<0,Sx>>Sy→Dz if DC=0,nop if DC=0 &...
Page 128 Section 2 CPU Table 2.42 Logical Shift Operation Instructions Instruction Operation Code Cycles DC Bit if Sy≥0,Sx<<Sy→Dz, clear Update PSHL Sx,Sy,Dz 111110********** LSW of Dz 10000001xxyyzzzz if Sy<0,Sx>>Sy→Dz, clear LSW of Dz if DC=1 & — DCT PSHL 111110********** Sy≥0,Sx<<Sy→Dz, clear Sx,Sy,Dz 10000010xxyyzzzz LSW of Dz...
Page 129 Section 2 CPU Table 2.43 System Control Instructions Instruction Operation Code Cycles DC Bit Dz→MACH — PLDS 111110********** Dz,MACH 111011010000zzzz Dz→MACL — PLDS 111110********** Dz,MACL 111111010000zzzz if DC=1,Dz→MACH — DCT PLDS 111110********** Dz,MACH if 0,nop 111011100000zzzz if DC=1,Dz→MACL — DCT PLDS 111110********** Dz,MACL if 0,nop...
Page 130 Section 2 CPU When there are no data transfer instructions being processed simultaneously in parallel with DSP operation instructions, it is possible to either write NOPX, NOPY instructions or to omit the instructions. The instruction codes are the same regardless of whether the NOPX, NOPY instructions are written or omitted.
Page 131: Usage Notes
Section 2 CPU Usage Notes 2.6.1 When not using DSP instructions When DSP instructions are not used, execute the following dummy instruction in the initialization section of application software in order to reduce the operating current. PCLR A0 : Clear the A0 register. PSHA #5, A0 : 5 bit shift to left.
Page 132 Section 2 CPU Rev. 2.00 Mar 09, 2006 page 106 of 906 REJ09B0292-0200...
Page 133: Section 3 Oscillator Circuits And Operating Modes
Section 3 Oscillator Circuits and Operating Modes Section 3 Oscillator Circuits and Operating Modes Overview Operation of the on-chip clock pulse generator, and CS0 area bus width specification, are controlled by the operating mode pins. A crystal resonator or external clock can be selected as the clock source.
Page 134 Section 3 Oscillator Circuits and Operating Modes Pin Configuration: Table 3.1 lists the functions relating to the pins relating to the oscillator circuit. Table 3.1 Pin Configuration Pin Name Function CKIO External clock input pin or internal clock output pin XTAL Connects to the crystal resonator EXTAL...
Page 135: Clock Operating Mode Settings
Section 3 Oscillator Circuits and Operating Modes 3.2.2 Clock Operating Mode Settings Table 3.2 lists the functions and operation of clock modes 0 to 6. Table 3.2 Operating Modes Clock Mode Function/Operation Clock Source PLL circuits 1 and 2 operate. A clock is output with the same Crystal resonator/ phase (with the same frequency as Eφ) as the internal clocks external clock input...
Page 136 Section 3 Oscillator Circuits and Operating Modes Clock Mode Function/Operation Clock Source Only PLL circuit 1 operates. Operate PLL circuit 1 when External clock input operating with a 1/4 φ cycle lag of the clock input from the CKIO pin and the internal clocks (Iφ, Eφ, Pφ) with respect to system clock φ.
Page 137 Section 3 Oscillator Circuits and Operating Modes Table 3.3 Clock Mode Pin Settings and States CKPREQ/ CKPREQ CKPREQ CKPREQ Clock Mode EXTAL XTAL CKIO Clock input Open Output/high Crystal Crystal impedance oscillation oscillation Clock input Open Output/high Crystal Crystal impedance oscillation oscillation Clock input...
Page 138: Connecting A Crystal Resonator
Section 3 Oscillator Circuits and Operating Modes 3.2.3 Connecting a Crystal Resonator Connecting a Crystal Resonator: Figure 3.2 shows an example of crystal resonator connection. The values of damping resistance R and load capacitances CL1 and CL2 should be decided after investigating the components in collaboration with the manufacturer of the crystal oscillator to be used.
Page 139: External Clock Input
Section 3 Oscillator Circuits and Operating Modes 3.2.4 External Clock Input An external clock is input from the EXTAL pin or the CKIO pin, depending on the clock mode. Clock Input from EXTAL Pin: This method can be used in clock modes 0, 1, 2, and 3. Ground level CKPREQ/CKM The CKIO pin is an output...
Page 140: Operating Frequency Selection By Register
Section 3 Oscillator Circuits and Operating Modes 3.2.5 Operating Frequency Selection by Register Using the frequency modification register (FMR), it is possible to specify the operating frequency division ratio for the internal clocks (Iφ, Eφ, Pφ). The internal clock frequency is determined under the control of PLL circuits 1 and 2 and dividers DIVM, DIVE, and DIVP.
Page 141 Section 3 Oscillator Circuits and Operating Modes Bit: PLL2ST PLL1ST CKIOST — Initial value: — — — — — R/W: Bit 7—PLL2ST: Switching is possible in modes 0 to 3. In modes 4 to 6, PLL circuit 2 cannot be used.
Page 142 Section 3 Oscillator Circuits and Operating Modes • Modes 0 and 1 PLL circuits 1 and 2 operating EXTAL input or crystal resonator used φ φ φ φ Iφ φ φ φ Eφ φ φ φ Pφ φ φ φ CKIO ×4 ×1...
Page 143 Section 3 Oscillator Circuits and Operating Modes • Modes 0 and 1 PLL circuit 1 operating, PLL circuit 2 halted EXTAL input or crystal resonator used φ φ φ φ Iφ φ φ φ Eφ φ φ φ Pφ φ φ φ CKIO ×4 ×1...
Page 144 Section 3 Oscillator Circuits and Operating Modes • Modes 0–6 PLL circuits 1 and 2 halted EXTAL input or crystal resonator used (modes 0–3) CKIO input (modes 4–6) φ φ φ φ Iφ φ φ φ Eφ φ φ φ Pφ...
Page 145 Section 3 Oscillator Circuits and Operating Modes Sample code for changing the frequency is shown below. SH7616 frequency change .equ h'fffffe90 WTCSR .equ h'fffffe80 RSTCSR .equ h'fffffe83 PACR .equ h'fffffc80 XRAM .equ h'1000e000 .export _init_FMR _init_FMR: mov.l #XRAM,r1 mov.l r1,r5 mov.l #FREQUENCY,r2...
Page 146 Section 3 Oscillator Circuits and Operating Modes MOV.L #WTCSR,R1 MOV.W #H'A51F,R2 MOV.L #H'26200000,R3 MOV.L #FMR,R4 clock4_err: clock4_err Main portion of frequency change code. First copy this to XRAM and then run it in XRAM. FREQUENCY: ; <Watchdog timer control and status register setting> ;...
Page 147 Section 3 Oscillator Circuits and Operating Modes ; Iφ (×4) = 62.5 MHz, Eφ (×4) = 62.5 MHz, ; Pφ (×2) = 31.25 MHz, CKIO (Eφ) = 62.5 MHz, #H'4E,R0 ; PLL circuits 1 and 2 → Enabled. ; Iφ (×4) = 62.5 MHz, Eφ (×2) = 31.25 MHz, ;...
Page 148: Clock Modes And Frequency Ranges
Section 3 Oscillator Circuits and Operating Modes If PLL circuit 1 or PLL circuit 2 does not become operational after modifying the frequency modification register (including modification in the operating state), it means that the above procedure or cautions have not been properly observed. In this case, the WDT will not operate even though the frequency modification register is modified.
Page 149: Notes On Board Design
Section 3 Oscillator Circuits and Operating Modes 3.2.7 Notes on Board Design When Using an External Crystal Oscillator: Place the crystal resonator, capacitors CL1 and CL2, and damping resistor R close to the EXTAL and XTAL pins. To prevent induction from interfering with correct oscillation, use a common grounding point for the capacitors connected to the resonator, and do not locate a wiring pattern near these components.
Page 150: Bus Width Of The Cs0 Area
Section 3 Oscillator Circuits and Operating Modes When Using a PLL Oscillator Circuit: Keep the wiring short from the PLL V and V connection pattern to the power supply pins, and make the pattern width large, to minimize the inductance component. Ground the oscillation stabilization capacitors C1 and C2 to V (PLL1) and V (PLL2), respectively.
Page 151: Section 4 Exception Handling
Section 4 Exception Handling Section 4 Exception Handling Overview 4.1.1 Types of Exception Handling and Priority Order Exception handling is initiated by four sources: resets, address errors, interrupts, and instructions (table 4.1). When several exception sources occur simultaneously, they are accepted and processed according to the priority order shown in table 4.1.
Page 152 Section 4 Exception Handling Table 4.1 Types of Exception Handling and Priority Order Exception Source Priority Reset Power-on reset High ↑ Manual reset Address CPU address error error DMA address error (DMAC and E-DMAC) Interrupt User break User debug interface (H-UDI) External interrupts (IRL1–IRL15, IRQ0–IRQ3 (set with IRL3, IRL2, IRL1, IRL0 pins)) On-chip peripheral modules...
Page 153: Exception Handling Operations
Section 4 Exception Handling 4.1.2 Exception Handling Operations Exception handling sources are detected, and exception handling started, according to the timing shown in table 4.2. Table 4.2 Timing of Exception Source Detection and Start of Exception Handling Exception Source Timing of Source Detection and Start of Handling Starts when the NMI pin is high and the RES pin changes from Reset Power-on reset...
Page 154: Exception Vector Table
Section 4 Exception Handling 4.1.3 Exception Vector Table Before exception handling begins, the exception vector table must be written in memory. The exception vector table stores the start addresses of exception service routines. (The reset exception table holds the initial values of PC and SP.) All exception sources are given different vector numbers and vector table address offsets, from which the vector table addresses are calculated.
Page 155 Section 4 Exception Handling Table 4.3 (b) Exception Processing Vector Table (IRQ Mode) Vector Vector Table Address Exception Source Number Offset Vector Addresses 64 * Interrupt IRQ0 H'00000100–H'00000103 65 * IRQ1 H'00000104–H'00000107 66 * IRQ2 H'00000108–H'0000010B 67 * IRQ3 H'0000010C–H'0000010F On-chip H'00000000–H'00000003 peripheral...
Page 156 Section 4 Exception Handling 2. External vector number fetches can be performed without using the auto-vector numbers in this table. 3. The vector numbers and vector table address offsets for each on-chip peripheral module interrupt are given table 5.4, Interrupt Exception Vectors and Priorities, in section 5, Interrupt Controller.
Page 157: Resets
Section 4 Exception Handling Resets 4.2.1 Types of Resets Resets have the highest priority of any exception source. There are two types of resets: manual resets and power-on resets. As table 4.5 shows, both types of resets initialize the internal status of the CPU.
Page 158: Manual Reset
Section 4 Exception Handling 4.2.3 Manual Reset When the NMI pin is low and the RES pin is driven low, the device executes a manual reset. For a reliable reset, the RES pin should be kept low for at least 20 clock cycles. During a manual reset, the CPU’s internal state is initialized.
Page 159 Section 4 Exception Handling Table 4.6 Bus Cycles and Address Errors Bus Cycle Type Master Bus Cycle Description Address Errors Instruction CPU Instruction fetched from even address None (normal) fetch Instruction fetched from odd address Address error occurs Instruction fetched from other than on-chip peripheral None (normal) module space Instruction fetched from on-chip peripheral module...
Page 160: Address Error Exception Handling
Section 4 Exception Handling 4.3.2 Address Error Exception Handling When an address error occurs, address error exception handling begins after the end of the bus cycle in which the error occurred and completion of the executing instruction. The CPU operates as follows: 1.
Page 161: Interrupts
Section 4 Exception Handling Interrupts 4.4.1 Interrupt Sources Table 4.7 shows the sources that initiate interrupt exception handling. These are divided into NMI, user breaks, H-UDI, IRL, IRQ, and on-chip peripheral modules. Table 4.7 Types of Interrupt Sources Type Request Source Number of Sources NMI pin (external input) User break...
Page 162: Interrupt Priority Levels
Section 4 Exception Handling 4.4.2 Interrupt Priority Levels The interrupt priority order is predetermined. When multiple interrupts occur simultaneously, the interrupt controller (INTC) determines their relative priorities and begins exception handling accordingly. The priority order of interrupts is expressed as priority levels 0–16, with priority 0 the lowest and priority 16 the highest.
Page 163: Exceptions Triggered By Instructions
Section 4 Exception Handling Exceptions Triggered by Instructions 4.5.1 Instruction-Triggered Exception Types Exception handling can be triggered by a trap instruction, general illegal instruction or illegal slot instruction, as shown in table 4.9. Table 4.9 Types of Exceptions Triggered by Instructions Type Source Instruction Comment...
Page 164: Illegal Slot Instructions
Section 4 Exception Handling 4.5.3 Illegal Slot Instructions An instruction placed immediately after a delayed branch instruction is said to be placed in a delay slot. If the instruction placed in the delay slot is undefined code, illegal slot exception handling begins when the undefined code is decoded.
Page 165: When Exception Sources Are Not Accepted
Section 4 Exception Handling When Exception Sources Are Not Accepted When an address error or interrupt is generated after a delayed branch instruction or interrupt- disabled instruction, it is sometimes not immediately accepted but is stored instead, as described in table 4.10.
Page 166: Instructions In Repeat Loops
Section 4 Exception Handling 4.6.3 Instructions in Repeat Loops If a repeat loop comprises up to three instructions, neither exceptions nor interrupts are accepted. If a repeat loop contains four or more instructions, neither exceptions nor interrupts are accepted during the execution cycle of the first instruction or the last three instructions. If a repeat loop contains four or more instructions, address errors only are accepted during the execution cycle of the fourth from last instruction.
Page 167: Stack Status After Exception Handling
Section 4 Exception Handling Stack Status after Exception Handling The status of the stack after exception handling ends is as shown in table 4.11. Table 4.11 Stack Status after Exception Handling Type Stack Status SP → Address of instruction after executed instruction Address error 32 bits 32 bits...
Page 168: Usage Notes
Section 4 Exception Handling Usage Notes 4.8.1 Value of Stack Pointer (SP) The value of the stack pointer must always be a multiple of four, otherwise an address error will occur when the stack is accessed during exception handling. 4.8.2 Value of Vector Base Register (VBR) The value of the vector base register must always be a multiple of four, otherwise an address error will occur when the vector table is accessed during exception handling.
Page 169: Section 5 Interrupt Controller (Intc)
Section 5 Interrupt Controller (INTC) Section 5 Interrupt Controller (INTC) Overview The interrupt controller (INTC) ascertains the priority order of interrupt sources and controls interrupt requests to the CPU. The INTC has registers for setting the priority of each interrupt which allow the user to set the order of priority in which interrupt requests are handled.
Page 170 Section 5 Interrupt Controller (INTC) IRL3–IRL0 A3–A0 Input/ output IVECF control D7–D0 Com- Interrupt request parator Priority decision logic (Interrupt request) (Interrupt request) H-UDI (Interrupt request) DMAC (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) SCIF (Interrupt request) (Interrupt request) (Interrupt request) E-DMAC (Including EtherC...
Page 171: Pin Configuration
Section 5 Interrupt Controller (INTC) 5.1.3 Pin Configuration Table 5.1 shows the INTC pin configuration. Table 5.1 Pin Configuration Name Abbreviation Function Nonmaskable interrupt input pin Input of nonmaskable interrupt request signal IRL3–IRL0 Level request interrupt input pins Input of maskable interrupt request signals Interrupt acceptance level output A3–A0...
Page 172: Interrupt Sources
7–4 in IRQCSR are cleared to 0. The initial value of bits other than 7–4 is 3. In the SH7616, VCRB is a reserved register and must not be accessed. 4. See section 11, Direct Memory Access Controlle for more information on VCRDMA0, and VCRDMA1.
Page 173: Nmi Interrupt
Section 5 Interrupt Controller (INTC) 5.2.1 NMI Interrupt The NMI interrupt has priority 16 and is always accepted. Input at the NMI pin is detected by edge. Use the NMI edge select bit (NMIE) in the interrupt control register (ICR) to select either the rising or falling edge.
Page 174: Irq Interrupts
Section 5 Interrupt Controller (INTC) 5.2.5 IRQ Interrupts An IRQ interrupt is requested when the external interrupt vector mode select bit (EXIMD) of the interrupt control register (ICR) is set to 1. An IRQ interrupt corresponds to input at one of pins IRL3–IRL0.
Page 175 Section 5 Interrupt Controller (INTC) An example of connections for external vector mode interrupts is shown in figure 5.2, and an example of connections for auto-vector mode interrupts in figure 5.3. Chip Priority Interrupt IRL0–IRL3 encoder requests IRL0–IRL3 Vector number A0–A3 generator IVECF...
Page 176 Section 5 Interrupt Controller (INTC) CKIO CS0–CS4 High A3–A0 Accepted interrupt level IVECF RD/WR D7–D0 Vector number input Figure 5.4 External Vector Fetch (Iφ φ φ φ : Eφ φ φ φ = 1 : 1) CKIO CS0–CS4 High Accepted interrupt level A3–A0 IVECF RD/WR...
Page 177 Section 5 Interrupt Controller (INTC) CKIO CS0–CS4 High A3–A0 Accepted interrupt level IVECF RD/WR Vector number input D7–D0 WAIT WAIT Input)) WAIT WAIT Figure 5.6 External Vector Fetch (Iφ φ φ φ : Eφ φ φ φ = 1 : 1 (WAIT CKIO CS0–CS4 High...
Page 178: On-Chip Peripheral Module Interrupts
Section 5 Interrupt Controller (INTC) 5.2.6 On-chip Peripheral Module Interrupts On-chip peripheral module interrupts are interrupts generated by the following 9 on-chip peripheral modules: • Direct memory access controller (DMAC) • Bus state controller (BSC) • Watchdog timer (WDT) • 16-bit free-running timer (FRT) •...
Page 179 Section 5 Interrupt Controller (INTC) sources occur simultaneously, their priority order is the default priority order indicated at the right in table 5.4. Table 5.4 (a) Interrupt Exception Vectors and Priority Order (IRL Mode) Interrupt Priority Vectors Priority within Vector Order Vector Table...
Page 180 Section 5 Interrupt Controller (INTC) Interrupt Priority Vectors Priority within Vector Order Vector Table (Initial IPR (Bit Setting VCR (Bit Default Interrupt Source Address Value) Numbers) Unit Numbers) Priority 0–127 * VBR + 15–0 (0) IPRA High VCRWDT High (vector No. (7–4) (14–8) ↑...
Page 181 4. Set to IRL1–IRL15 or IRQ0–IRQ3 by the EXIMD bit in ICR. 5. In the SH7616, VCRB is a reserved register and must not be accessed. 6. The E-DMAC interrupt (EINT) is the OR of those of the 19 interrupt sources in the EtherC/E-DMAC status register (EESR) that are enabled by the EtherC/E-DMAC status interrupt permission register (EESIPR).
Page 182 Section 5 Interrupt Controller (INTC) Table 5.4 (b) Interrupt Exception Vectors and Priority Order (IRQ Mode) Interrupt Priority Vectors Priority within Vector Order Vector Table (Initial IPR (Bit Setting VCR (Bit Default Interrupt Source Address Value) Numbers) Unit Numbers) Priority VBR + —...
Page 183 Section 5 Interrupt Controller (INTC) Interrupt Priority Vectors Priority within Vector Order Vector Table (Initial IPR (Bit Setting VCR (Bit Default Interrupt Source Address Value) Numbers) Unit Numbers) Priority E-DMAC EINT * 0–127 * VBR + 15–0 (0) IPRB High VCRA (14–8) High (vector No.
Page 184 4. Set to IRL1–IRL15 or IRQ0–IRQ3 by the EXIMD bit in ICR. 5. In the SH7616, VCRB is a reserved register and must not be accessed. 6. The E-DMAC interrupt (EINT) is the OR of those of the 19 interrupt sources in the EtherC/E-DMAC status register (EESR) that are enabled by the EtherC/E-DMAC status interrupt permission register (EESIPR).
Page 185: Register Descriptions
Section 5 Interrupt Controller (INTC) Register Descriptions 5.3.1 Interrupt Priority Level Setting Register A (IPRA) Interrupt priority level setting register A (IPRA) is a 16-bit read/write register that assigns priority levels from 0 to 15 to on-chip peripheral module interrupts. IPRA is initialized to H'0000 by a reset.
Page 186: Interrupt Priority Level Setting Register B (Iprb)
Section 5 Interrupt Controller (INTC) 5.3.2 Interrupt Priority Level Setting Register B (IPRB) Interrupt priority level setting register B (IPRB) is a 16-bit read/write register that assigns priority levels from 0 to 15 to on-chip peripheral module interrupts. IPRB is initialized to H'0000 by a reset.
Page 187: Interrupt Priority Level Setting Register C (Iprc)
Section 5 Interrupt Controller (INTC) 5.3.3 Interrupt Priority Level Setting Register C (IPRC) Interrupt priority level setting register C (IPRC) is a 16-bit read/write register that sets the priority levels (0–15) of IRQ0–IRQ3 interrupts. IPRC is initialized to H'0000 by a reset. It is not initialized in standby mode.
Page 188: Interrupt Priority Level Setting Register D (Iprd)
Section 5 Interrupt Controller (INTC) 5.3.4 Interrupt Priority Level Setting Register D (IPRD) Interrupt priority level setting register D (IPRD) is a 16-bit read/write register that sets the priority levels (0–15) of on-chip peripheral module interrupts. IPRD is initialized to H'0000 by a reset. It is not initialized in standby mode.
Page 189: Interrupt Priority Level Setting Register E (Ipre)
Section 5 Interrupt Controller (INTC) 5.3.5 Interrupt Priority Level Setting Register E (IPRE) Interrupt priority level setting register E (IPRE) is a 16-bit read/write register that sets the priority levels (0–15) of on-chip peripheral module interrupts. IPRE is initialized to H'0000 by a reset. It is not initialized in standby mode.
Page 190: Vector Number Setting Register Wdt (Vcrwdt)
Section 5 Interrupt Controller (INTC) Table 5.5 Interrupt Request Sources and IPRA–IPRE Register Bits 15 to 12 Bits 11 to 8 Bits 7 to 4 Bits 3 to 0 Interrupt priority level setting Reserved DMAC0, WDT, REF Reserved register A DMAC1 Interrupt priority level setting E-DMAC...
Page 191: Vector Number Setting Register A (Vcra)
Section 5 Interrupt Controller (INTC) Bits 14 to 8—Watchdog Timer (WDT) Interval Interrupt Vector Number 6 to 0 (WITV6– WITV0): These bits set the vector number for the interval interrupt (ITI) of the watchdog timer (WDT). There are seven bits, so the value can be set between 0 and 127. Bits 6 to 0—Bus State Controller (BSC) Compare Match Interrupt Vector Number 6 to 0 (BCMV6–BCMV0): These bits set the vector number for the compare match interrupt (CMI) of the bus state controller (BSC).
Page 192: Vector Number Setting Register B (Vcrb)
Section 5 Interrupt Controller (INTC) 5.3.8 Vector Number Setting Register B (VCRB) Vector number setting register B (VCRB) is a 16-bit reserved register. Access to this register is prohibited. VCRB is initialized to H'0000 by a reset. It is not initialized in standby mode. Bit: —...
Page 193: Vector Number Setting Register D (Vcrd)
Section 5 Interrupt Controller (INTC) Bits 6 to 0—16-Bit Free-Running Timer (FRT) Output-Compare Interrupt Vector Number 6 to 0 (FOCV6–FOCV0): These bits set the vector number for the 16-bit free-running timer (FRT) output-compare interrupt (OCI). There are seven bits, so the value can be set between 0 and 127. 5.3.10 Vector Number Setting Register D (VCRD) Vector number setting register D (VCRD) is a 16-bit read/write register that sets the 16-bit free-...
Page 194: Vector Number Setting Register E (Vcre)
Section 5 Interrupt Controller (INTC) 5.3.11 Vector Number Setting Register E (VCRE) Vector number setting register E (VCRE) is a 16-bit read/write register that sets the 16-bit timer pulse unit 0 (TPU0) TGR0A and TGR0B input capture/compare match interrupt vector numbers (0–127).
Page 195: Vector Number Setting Register F (Vcrf)
Section 5 Interrupt Controller (INTC) 5.3.12 Vector Number Setting Register F (VCRF) Vector number setting register F (VCRF) is a 16-bit read/write register that sets the 16-bit timer pulse unit 0 (TPU0) TGR0C and TGR0D input capture/compare match interrupt vector numbers (0–127).
Page 196: Vector Number Setting Register G (Vcrg)
Section 5 Interrupt Controller (INTC) 5.3.13 Vector Number Setting Register G (VCRG) Vector number setting register G (VCRG) is a 16-bit read/write register that sets the 16-bit timer pulse unit 0 (TPU0) TCNT0 overflow interrupt vector number (0–127). VCRG is initialized to H'0000 by a reset. It is not initialized in standby mode. Bit: —...
Page 197: Vector Number Setting Register H (Vcrh)
Section 5 Interrupt Controller (INTC) 5.3.14 Vector Number Setting Register H (VCRH) Vector number setting register H (VCRH) is a 16-bit read/write register that sets the 16-bit timer pulse unit 1 (TPU1) TGR1A and TGR1B input capture/compare match interrupt vector numbers (0–127).
Page 198: Vector Number Setting Register I (Vcri)
Section 5 Interrupt Controller (INTC) 5.3.15 Vector Number Setting Register I (VCRI) Vector number setting register I (VCRI) is a 16-bit read/write register that sets the 16-bit timer pulse unit 1 (TPU1) TCNT1 overflow/underflow interrupt vector numbers (0–127). VCRI is initialized to H'0000 by a reset. It is not initialized in standby mode. Bit: —...
Page 199: Vector Number Setting Register J (Vcrj)
Section 5 Interrupt Controller (INTC) 5.3.16 Vector Number Setting Register J (VCRJ) Vector number setting register J (VCRJ) is a 16-bit read/write register that sets the 16-bit timer pulse unit 2 (TPU2) TGR2A and TGR2B input capture/compare match interrupt vector numbers (0–127).
Page 200: Vector Number Setting Register K (Vcrk)
Section 5 Interrupt Controller (INTC) 5.3.17 Vector Number Setting Register K (VCRK) Vector number setting register K (VCRK) is a 16-bit read/write register that sets the 16-bit timer pulse unit 2 (TPU2) TCNT2 overflow/underflow interrupt vector numbers (0–127). VCRK is initialized to H'0000 by a reset. It is not initialized in standby mode. Bit: —...
Page 201: Vector Number Setting Register L (Vcrl)
Section 5 Interrupt Controller (INTC) 5.3.18 Vector Number Setting Register L (VCRL) Vector number setting register L (VCRL) is a 16-bit read/write register that sets the serial communication interface with FIFO 1 (SCIF1) receive-error interrupt and receive-data-full/data- ready interrupt vector numbers (0–127). VCRL is initialized to H'0000 by a reset.
Page 202: Vector Number Setting Register M (Vcrm)
Section 5 Interrupt Controller (INTC) 5.3.19 Vector Number Setting Register M (VCRM) Vector number setting register M (VCRM) is a 16-bit read/write register that sets the serial communication interface with FIFO 1 (SCIF1) break interrupt and transmit-data-empty interrupt vector numbers (0–127). VCRM is initialized to H'0000 by a reset.
Page 203: Vector Number Setting Register N (Vcrn)
Section 5 Interrupt Controller (INTC) 5.3.20 Vector Number Setting Register N (VCRN) Vector number setting register N (VCRN) is a 16-bit read/write register that sets the serial communication interface with FIFO 2 (SCIF2) receive-error interrupt and receive-data-full/data- ready interrupt vector numbers (0–127). VCRN is initialized to H'0000 by a reset.
Page 204: Vector Number Setting Register O (Vcro)
Section 5 Interrupt Controller (INTC) 5.3.21 Vector Number Setting Register O (VCRO) Vector number setting register O (VCRO) is a 16-bit read/write register that sets the serial communication interface with FIFO 2 (SCIF2) break interrupt and transmit-data-empty interrupt vector numbers (0–127). VCRO is initialized to H'0000 by a reset.
Page 205: Vector Number Setting Register P (Vcrp)
Section 5 Interrupt Controller (INTC) 5.3.22 Vector Number Setting Register P (VCRP) Vector number setting register P (VCRP) is a 16-bit read/write register that sets the serial I/O with FIFO (SIOF) receive overrun error interrupt and transmit underrun error interrupt vector numbers (0–127).
Page 206: Vector Number Setting Register Q (Vcrq)
Section 5 Interrupt Controller (INTC) 5.3.23 Vector Number Setting Register Q (VCRQ) Vector number setting register Q (VCRQ) is a 16-bit read/write register that sets the serial I/O with FIFO (SIOF) receive-data-full interrupt and transmit-data-empty interrupt vector numbers (0– 127). VCRQ is initialized to H'0000 by a reset.
Page 207: Vector Number Setting Register R (Vcrr)
Section 5 Interrupt Controller (INTC) 5.3.24 Vector Number Setting Register R (VCRR) Vector number setting register R (VCRR) is a 16-bit read/write register that sets the serial I/O 1 (SIO1) receive overrun error interrupt and transmit underrun error interrupt vector numbers (0– 127).
Page 208: Vector Number Setting Register S (Vcrs)
Section 5 Interrupt Controller (INTC) 5.3.25 Vector Number Setting Register S (VCRS) Vector number setting register S (VCRS) is a 16-bit read/write register that sets the serial I/O 1 (SIO1) receive-data-full interrupt and transmit-data-empty interrupt vector numbers (0–127). VCRS is initialized to H'0000 by a reset. It is not initialized in standby mode. Bit: —...
Page 209: Vector Number Setting Register T (Vcrt)
Section 5 Interrupt Controller (INTC) 5.3.26 Vector Number Setting Register T (VCRT) Vector number setting register T (VCRT) is a 16-bit read/write register that sets the serial I/O 2 (SIO2) receive overrun error interrupt and transmit underrun error interrupt vector numbers (0– 127).
Page 210: Vector Number Setting Register U (Vcru)
Section 5 Interrupt Controller (INTC) 5.3.27 Vector Number Setting Register U (VCRU) Vector number setting register U (VCRU) is a 16-bit read/write register that sets the serial I/O 2 (SIO2) receive-data-full interrupt and transmit-data-empty interrupt vector numbers (0–127). VCRU is initialized to H'0000 by a reset. It is not initialized in standby mode. Bit: —...
Page 211 Section 5 Interrupt Controller (INTC) Table 5.6 Interrupt Request Sources and Vector Number Setting Registers (1) Bits Register 14–8 6–0 Vector number setting register Interval interrupt (WDT) Compare-match interrupt (BSC) Vector number setting register A E-DMAC interrupt (E-DMAC) Reserved Vector number setting register B Reserved Reserved Vector number setting register C...
Page 212 Section 5 Interrupt Controller (INTC) Bits Register 14–8 6–0 Vector number setting register R Receive overrun error interrupt Transmit underrun error (SIO1) interrupt (SIO1) Vector number setting register S Receive-data-full interrupt Transmit-data-empty interrupt (SIO1) (SIO1) Vector number setting register T Receive overrun error interrupt Transmit underrun error (SIO2)
Page 213: Interrupt Control Register (Icr)
Section 5 Interrupt Controller (INTC) 5.3.28 Interrupt Control Register (ICR) ICR is a 16-bit register that sets the input signal detection mode of external interrupt input pin NMI and indicates the input signal level at the NMI pin. It can also specify IRQ or IRL mode by means of the External Interrupt Vector Mode Select bit.
Page 214: Irq Control/Status Register (Irqcsr)
Section 5 Interrupt Controller (INTC) Bit 1—External Interrupt Vector Mode Select (EXIMD): This bit selects IRQ mode or IRL mode. In IRQ mode, each of signals IRL3 to IRL0 functions as a separate interrupt source. In IRL mode, these signals can specify interrupt priority levels 1 to 15. Bit 1: EXIMD Description IRL mode...
Page 215 Section 5 Interrupt Controller (INTC) Bits 15 to 8—IRQ Sense Select Bits (IRQ31S–IRQ00S): These bits set the IRQ detection mode for IRL3–IRL0. Bit 15–8: Bit 15–8: IRQn1S IRQn0S Description Low-level detection (Initial value) Rising-edge detection Falling-edge detection Both-edge detection Note: n = 0 to 3 Bits 7 to 4—IRL Pin Status Bits (IRL3PS–IRL0PS): These bits indicate the IRL3–IRL0 pin status.
Page 216: Interrupt Operation
Section 5 Interrupt Controller (INTC) Interrupt Operation 5.4.1 Interrupt Sequence The sequence of operations in interrupt generation is described below and illustrated in figure 5.8. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest-priority interrupt among the interrupt requests sent, according to the priority levels set in interrupt priority level setting registers A to E (IPRA–...
Page 217 Section 5 Interrupt Controller (INTC) Program execution state Interrupt generated? NMI? User break? H-UDI interrupt? Level 15 interrupt? Level 14 interrupt? I3 to I0 ≤ level 14? Level 1 Save SR to stack interrupt? I3 to I0 ≤ Save PC to stack level 13? I3 to I0 = Copy accepted...
Page 218: Stack State After Interrupt Exception Handling
Section 5 Interrupt Controller (INTC) 5.4.2 Stack State after Interrupt Exception Handling The state of the stack after interrupt exception handling is completed is shown in figure 5.9. Address 4n-8 32 bits 4n-4 32 bits PC: Start address of return destination instruction (instruction after executing instruction) Figure 5.9 Stack State after Interrupt Exception Handling Interrupt Response Time Table 5.8 shows the interrupt response time, which is the time from the occurrence of an interrupt...
Page 219 Section 5 Interrupt Controller (INTC) Table 5.8 Interrupt Response Time Number of States Peripheral Module Item IRL/IRQ Notes 2.0 × Icyc 0.5 × Icyc 0.5 × Icyc 1.0 × Pcyc Compare identified + 1.0 × Ecyc + 1.0 × Pcyc interrupt priority with SR + 1.5 ×...
Page 220: Sampling Of Pins Irl3-Irl0
Section 5 Interrupt Controller (INTC) Sampling of Pins IRL3 IRL3 IRL3–IRL0 IRL3 IRL0 IRL0 IRL0 Signals on interrupt pins IRL3 to IRL0 pass through the noise canceler before being sent by the interrupt controller to the CPU as interrupt requests, as shown in figure 5.10. The noise canceler cancels noise that changes in short cycles.
Page 221: Usage Notes
Section 5 Interrupt Controller (INTC) Usage Notes 1. Note on module standby execution Do not execute module standby for modules that have the module standby function when the possibility remains that an interrupt request may be output. 2. Notes on interrupt source clearing A.
Page 222 Section 5 Interrupt Controller (INTC) Write completed Next interrupt can be accepted External write Interrupt clear instruction cycle External read Synchronization instruction cycle RTE instruction Delay slot instruction Interrupt return destination instruction 0.5Icyc + 1.0Ecyc + 1.5Pcyc IRL3–IRL0 F: Instruction fetch ....Instruction is fetched from memory in which program is stored D: Instruction decode ...
Page 223 Section 5 Interrupt Controller (INTC) B. When clearing on-chip interrupt source When an interrupt source is from an on-chip peripheral module, also, pipeline operation must be considered to ensure that the same interrupt is not implemented again. An interval of 0.5 Icyc + 1.0 Pcyc is required until an on-chip peripheral module interrupt is identified by the CPU.
Page 224 Section 5 Interrupt Controller (INTC) Write completed Next interrupt can be accepted On-chip peripheral Interrupt clear instruction write, min. 1 Icyc On-chip peripheral Synchronization instruction read, min. 1 Icyc • • • LDC instruction Interrupt disable instruction Normal instruction 0.5Icyc + 1.0Pcyc On-chip peripheral interrupt Figure 5.14 Pipeline Operation when Interrupts are Enabled by Means of SR Modification In the above figure, the stage in which the instruction fetch occurs cannot be specified because...
Page 225: Section 6 User Break Controller (Ubc)
Section 6 User Break Controller (UBC) Section 6 User Break Controller (UBC) Overview The user break controller (UBC) provides functions that simplify program debugging. When break conditions are set in the UBC, a user break interrupt is generated according to the conditions of the bus cycle generated by the CPU or on-chip DMAC (DMAC or E-DMAC).
Page 226: Block Diagram
Section 6 User Break Controller (UBC) The branch source/branch destination can be traced when a branch instruction is fetched (maximum 8 addresses (4 pairs)). 6.1.2 Block Diagram BARAH BARAL Address BAMRAH BAMRAL Access BBRA Channel A BARBH BARBL Address BAMRBH BAMRBL Access BBRB Channel B...
Page 227: Register Configuration
Section 6 User Break Controller (UBC) 6.1.3 Register Configuration Table 6.1 UBC Registers Abbre- Initial Value * Access Size * Name viation Address Break address register AH BARAH H'0000 H'FFFFFF00 Break address register AL BARAL H'0000 H'FFFFFF02 Break address mask register AH BAMRAH H'0000 H'FFFFFF04...
Page 228 Section 6 User Break Controller (UBC) Abbre- Initial Value * Access Size * Name viation Address Break bus cycle register D BBRD H'0000 H'FFFFFF68 16, 32 Break execution times register D BETRD H'0000 H'FFFFFF78 16, 32 Break control register H BRCRH H'0000 H'FFFFFF30...
Page 229: Register Descriptions
Section 6 User Break Controller (UBC) Register Descriptions 6.2.1 Break Address Register A (BARA) BARAH Bit: BAA31 BAA30 BAA29 BAA28 BAA27 BAA26 BAA25 BAA24 Initial value: R/W: Bit: BAA23 BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16 Initial value: R/W: BARAL Bit: BAA15 BAA14...
Page 230: Break Address Mask Register A (Bamra)
Section 6 User Break Controller (UBC) 6.2.2 Break Address Mask Register A (BAMRA) BAMRAH Bit: BAMA31 BAMA30 BAMA29 BAMA28 BAMA27 BAMA26 BAMA25 BAMA24 Initial value: R/W: Bit: BAMA23 BAMA22 BAMA21 BAMA20 BAMA19 BAMA18 BAMA17 BAMA16 Initial value: R/W: BAMRAL Bit: BAMA15 BAMA14 BAMA13 BAMA12 BAMA11 BAMA10 BAMA9 BAMA8 Initial value:...
Page 231: Break Bus Cycle Register A (Bbra)
Section 6 User Break Controller (UBC) BAMRAL Bits 15 to 0—Break Address Mask A15 to A0 (BAMA15 to BAMA0): These bits specify whether or not corresponding channel A break address bits 15 to 0 (BAA15 to BAA0) set in BARAL are to be masked. Bit 31 to 0: BAMAn Description...
Page 232 Section 6 User Break Controller (UBC) Bits 5 and 4—Instruction Fetch/Data Access Select A (IDA1, IDA0): These bits specify whether an instruction fetch cycle or data access cycle is to be selected as the bus cycle used as a channel A break condition.
Page 233: Break Address Register B (Barb)
Section 6 User Break Controller (UBC) 6.2.4 Break Address Register B (BARB) BARBH Bit: BAB31 BAB30 BAB29 BAB28 BAB27 BAB26 BAB25 BAB24 Initial value: R/W: Bit: BAB23 BAB22 BAB21 BAB20 BAB19 BAB18 BAB17 BAB16 Initial value: R/W: BARBL Bit: BAB15 BAB14 BAB13 BAB12...
Page 234: Break Address Mask Register B (Bamrb)
Section 6 User Break Controller (UBC) 6.2.5 Break Address Mask Register B (BAMRB) BAMRBH Bit: BAMB31 BAMB30 BAMB29 BAMB28 BAMB27 BAMB26 BAMB25 BAMB24 Initial value: R/W: Bit: BAMB23 BAMB22 BAMB21 BAMB20 BAMB19 BAMB18 BAMB17 BAMB16 Initial value: R/W: BAMRBL Bit: BAMB15 BAMB14 BAMB13 BAMB12 BAMB11 BAMB10 BAMB9 BAMB8 Initial value:...
Page 235: Break Bus Cycle Register B (Bbrb)
Section 6 User Break Controller (UBC) BAMRBL Bits 15 to 0—Break Address Mask B15 to B0 (BAMB15 to BAMB0): These bits specify whether or not corresponding channel B break address bits 15 to 0 (BAB15 to BAB0) set in BARBL are to be masked. Bit 31 to 0: BAMBn Description...
Page 236 Section 6 User Break Controller (UBC) Bits 5 and 4—Instruction Fetch/Data Access Select B (IDB1, IDB0): These bits specify whether an instruction fetch cycle or data access cycle is to be selected as the bus cycle used as a channel B break condition.
Page 237: Break Address Register C (Barc)
Section 6 User Break Controller (UBC) 6.2.7 Break Address Register C (BARC) BARCH Bit: BAC31 BAC30 BAC29 BAC28 BAC27 BAC26 BAC25 BAC24 Initial value: R/W: Bit: BAC23 BAC22 BAC21 BAC20 BAC19 BAC18 BAC17 BAC16 Initial value: R/W: BARCL Bit: BAC15 BAC14 BAC13 BAC12...
Page 238: Break Address Mask Register C (Bamrc)
Section 6 User Break Controller (UBC) BARC Configuration Upper 16 Bits Lower 16 Bits (BAC31 to BAC16) (BAC15 to BAC0) XYEC = 0 Address Upper 16 bits of address bus Lower 16 bits of address bus XYEC = 1 X address X address —...
Page 239 Section 6 User Break Controller (UBC) Break address mask register C (BAMRC) consists of two 16-bit readable/writable registers: break address mask register CH (BAMRCH) and break address mask register CL (BAMRCL). BAMRCH specifies which bits of the break address set in BARCH are to be masked, and BAMRCL specifies which bits of the break address set in BARCL are to be masked.
Page 240: Break Data Register C (Bdrc)
Section 6 User Break Controller (UBC) 6.2.9 Break Data Register C (BDRC) BDRCH Bit: BDC31 BDC30 BDC29 BDC28 BDC27 BDC26 BDC25 BDC24 Initial value: R/W: Bit: BDC23 BDC22 BDC21 BDC20 BDC19 BDC18 BDC17 BDC16 Initial value: R/W: BDRCL Bit: BDC15 BDC14 BDC13 BDC12...
Page 241: Break Data Mask Register C (Bdmrc)
Section 6 User Break Controller (UBC) BDRC Configuration Upper 16 Bits Lower 16 Bits (BDC31 to BDC16) (BDC15 to BDC0) XYEC = 0 Data Upper 16 bits of data bus Lower 16 bits of data bus XYEC = 1 X data X data —...
Page 242 Section 6 User Break Controller (UBC) which bits of the break data set in BDRCL are to be masked. Operation also depends on bits XYEC and XYSC in BBRC as shown below. BDMRCH and BDMRCL are initialized to H'0000 by a power-on reset; after a manual reset, their values are undefined. BDMRC Configuration Upper 16 Bits Lower 16 Bits...
Page 243: Break Bus Cycle Register C (Bbrc)
Section 6 User Break Controller (UBC) 6.2.11 Break Bus Cycle Register C (BBRC) Bit: — — — — — — XYEC XYSC Initial value: R/W: Bit: CPC1 CPC0 IDC1 IDC0 RWC1 RWC0 SZC1 SZC0 Initial value: R/W: Break bus cycle register C (BBRC) is a 16-bit readable/writable register that sets five channel C break conditions: (1) internal bus (C-bus, I-bus)/X memory bus/Y memory bus), (2) CPU cycle/on-chip DMAC (DMAC, E-DMAC) cycle, (3) instruction fetch/data access, (4) read/write, and (5) operand size.
Page 244: Break Execution Times Register C (Betrc)
Section 6 User Break Controller (UBC) 6.2.12 Break Execution Times Register C (BETRC) Bit: — — — — ETRC11 ETRC10 ETRC9 ETRC8 Initial value: R/W: Bit: ETRC7 ETRC6 ETRC5 ETRC4 ETRC3 ETRC2 ETRC1 ETRC0 Initial value: R/W: When a channel C execution-times break condition is enabled (by setting the ETBEC bit in BRCR), this 16-bit register specifies the number of times a channel C break condition occurs before a user break interrupt is requested.
Page 245: Break Address Register D (Bard)
Section 6 User Break Controller (UBC) 6.2.13 Break Address Register D (BARD) BARDH BAD31 BAD30 BAD29 BAD28 BAD27 BAD26 BAD25 BAD24 Initial value Read/Write BAD23 BAD22 BAD21 BAD20 BAD19 BAD18 BAD17 BAD16 Initial value Read/Write BARDL BAD15 BAD14 BAD13 BAD12 BAD11 BAD10 BAD9...
Page 246: Break Address Mask Register D (Bamrd)
Section 6 User Break Controller (UBC) BARD Configuration Upper 16 Bits Lower 16 Bits (BAD31 to BAD16) (BAD15 to BAD0) XYED = 0 Address Upper 16 bits of address bus Lower 16 bits of address bus XYED = 1 X address X address —...
Page 247 Section 6 User Break Controller (UBC) Break address mask register D (BAMRD) consists of two 16-bit readable/writable registers: break address mask register DH (BAMRDH) and break address mask register DL (BAMRDL). BAMRDH specifies which bits of the break address set in BARDH are to be masked, and BAMRDL specifies which bits of the break address set in BARDL are to be masked.
Page 248: Break Data Register D (Bdrd)
Section 6 User Break Controller (UBC) 6.2.15 Break Data Register D (BDRD) BDRDH Bit: BDD31 BDD30 BDD29 BDD28 BDD27 BDD26 BDD25 BDD24 Initial value: R/W: Bit: BDD23 BDD22 BDD21 BDD20 BDD19 BDD18 BDD17 BDD16 Initial value: R/W: BDRDL Bit: BDD15 BDD14 BDD13 BDD12...
Page 249: Break Data Mask Register D (Bdmrd)
Section 6 User Break Controller (UBC) BDRD Configuration Upper 16 Bits Lower 16 Bits (BDD31 to BDD16) (BDD15 to BDD0) XYED = 0 Data Upper 16 bits of data bus Lower 16 bits of data bus XYED = 1 X data X data —...
Page 250 Section 6 User Break Controller (UBC) specifies which bits of the break data set in BDRDH are to be masked, and BDMRDL specifies which bits of the break data set in BDRDL are to be masked. Operation also depends on bits XYED and XYSD in BBRD as shown below.
Page 251: Break Bus Cycle Register D (Bbrd)
Section 6 User Break Controller (UBC) 6.2.17 Break Bus Cycle Register D (BBRD) Bit: — — — — — — XYED XYSD Initial value: R/W: Bit: CPD1 CPD0 IDD1 IDD0 RWD1 RWD0 SZD1 SZD0 Initial value: R/W: Break bus cycle register D (BBRD) is a 16-bit readable/writable register that sets five channel D break conditions: (1) internal bus (C-bus, I-bus)/X memory bus/Y memory bus), (2) CPU cycle/on-chip DMAC (DMAC, E-DMAC) cycle, (3) instruction fetch/data access, (4) read/write, and (5) operand size.
Page 252: Break Execution Times Register D (Betrd)
Section 6 User Break Controller (UBC) 6.2.18 Break Execution Times Register D (BETRD) Bit: — — — — ETRD11 ETRD10 ETRD9 ETRD8 Initial value: R/W: Bit: ETRD7 ETRD6 ETRD5 ETRD4 ETRD3 ETRD2 ETRD1 ETRD0 Initial value: R/W: When a channel D execution-times break condition is enabled (by setting the ETBED bit in BRCR), this 16-bit register specifies the number of times a channel D break condition occurs before a user break interrupt is requested.
Page 253: Break Control Register (Brcr)
Section 6 User Break Controller (UBC) 6.2.19 Break Control Register (BRCR) BRCRH Bit: CMFCA CMFPA — — PCTE PCBA — — Initial value: R/W: Bit: CMFCB CMFPB — SEQ1 SEQ0 PCBB — — Initial value: R/W: BRCRL Bit: CMFCC CMFPC ETBEC —...
Page 254 Section 6 User Break Controller (UBC) Bit 31—CPU Condition Match Flag A (CMFCA): This flag is set to 1 when a CPU bus cycle condition, among the break conditions set for channel A, is satisfied. This flag is not cleared to 0 (if the flag setting is to be checked again after it has once been set, the flag must be cleared by a write).
Page 255 Section 6 User Break Controller (UBC) Bit 23—CPU Condition Match Flag B (CMFCB): This flag is set to 1 when a CPU bus cycle condition, among the break conditions set for channel B, is satisfied. This flag is not cleared to 0 (if the flag setting is to be checked again after it has once been set, the flag must be cleared by a write).
Page 256 Section 6 User Break Controller (UBC) Bit 18—PC Break Select B (PCBB): Selects whether a channel B instruction fetch cycle break is effected before or after execution of the instruction. Bit 18: PCBB Description Channel B instruction fetch cycle break is effected before instruction execution (Initial value) Channel B instruction fetch cycle break is effected after instruction execution Bits 17 and 16—Reserved: These bits are always read as 0.
Page 257 Section 6 User Break Controller (UBC) Bit 12—Reserved: This bit is always read as 0. The write value should always be 0. Bit 11—Data Break Enable C (DBEC): Selects whether a data bus condition is to be included in the channel C break conditions. Bit 11: DBEC Description Data bus condition is not included in channel C conditions...
Page 258 Section 6 User Break Controller (UBC) Bit 5—Execution-Times Break Enable D (ETBED): Enables a channel D execution-times break condition. When this bit is 1, a user break interrupt is generated when the number of break conditions that have occurred equals the number of executions specified by the break execution times register (BETRD).
Page 259: Branch Flag Registers (Brfr)
Section 6 User Break Controller (UBC) 6.2.20 Branch Flag Registers (BRFR) Bit: PID2 PID1 PID0 — — — — Initial value: Undefined Undefined Undefined R/W: Bit: — — — — — — — Initial value: R/W: The branch flag registers (BRFR) comprise a set of four 16-bit read-only registers. The BRFR registers contain flags indicating whether the actual branch addresses (in a branch instruction, repeat, interrupt, etc.) have been saved in BRSR and BRDR, and a 3-bit pointer indicating the number of cycles from fetch to execution of the last instruction executed.
Page 260: Branch Source Registers (Brsr)
Section 6 User Break Controller (UBC) Bit 7—Destination Verify Flag (DVF): Indicates whether the branch source address has been stored in BRDR. This flag is set when the instruction at the branch destination address is fetched, and reset when BRDR is read. Bit 7: DVF Description BRDR value is invalid...
Page 261: Branch Destination Registers (Brdr)
Section 6 User Break Controller (UBC) The branch source registers (BRSR) comprise a set of four 32-bit read-only registers. The values in these registers are used to calculate the address of the last instruction executed before a branch when performing a PC trace. The BRSR registers form a FIFO (first-in first-out) queue for PC trace use.
Page 262: Operation
Section 6 User Break Controller (UBC) Operation 6.3.1 User Break Operation Sequence The sequence of operations from setting of break conditions to user break interrupt exception handling is described below. 1. Set the break address in the break address register (BARA/BARB/BARC/BARD), the bits to be masked in the break address mask register (BAMRA/BAMRB/BAMRC/BAMRD), the break bits in the break data register (BDRC/BDRD), and the data to be masked in the break data mask register (BDMRC/BDMRD).
Page 263: Instruction Fetch Cycle Break
Section 6 User Break Controller (UBC) 6.3.2 Instruction Fetch Cycle Break 1. If a CPU/instruction fetch/read/word setting is made in the break bus cycle register (BBRA, BBRB, BBRC, or BBRD), a CPU instruction fetch cycle can be selected as a break condition. In this case, it is possible to specify whether the break is to be effected before or after execution of the relevant instruction by means of the PCBA/PCBB/PCBC/PCBD bit in the break control register (BRCR).
Page 264: Data Access Cycle Break
Section 6 User Break Controller (UBC) 6.3.3 Data Access Cycle Break 1. Memory cycles for which a CPU data access break can be set are memory cycles due to instructions and stack operations and vector reads when exception handling is executed. A CPU data access break cannot be set for a vector fetch cycle of an external vector interrupt, for burst write of a synchronous DRAM, or for a dammy access cycle of a single read.
Page 265: Saved Program Counter (Pc) Value
Section 6 User Break Controller (UBC) 6.3.4 Saved Program Counter (PC) Value 1. When instruction fetch (pre-instruction-execution) is set as break condition The program counter (PC) value saved to the stack in user break interrupt exception handling is the address of the instruction for which the break condition matched. In this case, the fetched instruction is not executed, a user break interrupt being generated prior to its execution.
Page 266: Sequential Break
Section 6 User Break Controller (UBC) 6.3.6 Sequential Break Channel C to Channel D: When SEQ1 in BRCR is set to 0 and SEQ0 is set to 1, a sequential break occurs when the conditions are met for channel C and then channel D, in that order. This causes the BRCR condition match flag for each channel to be set to 1.
Page 267: Pc Traces
Section 6 User Break Controller (UBC) If the break conditions for channels C and D are met at the same time, and the conditions had not already been met for channel C, the conditions are considered to be met for channel C. Also, if the conditions for channel C have already been met when the break conditions for channels C and D are met at the same time, the conditions for channel D are considered to be met and a break occurs.
Page 268 Section 6 User Break Controller (UBC) Exec: branch Dest Not executed Dest: instr; Interrupt Int: interrupt routine Figure 6.2 When Interrupt Occurs before Branch Instruction Is Executed Table 6.3 BSA Values Stored in Exception Handling before Execution of Branch Destination Instruction Branch Destination Branch Source Address Calculable by Means Branch...
Page 269: Examples Of Use
Section 6 User Break Controller (UBC) 4. BRSR, BRDR, and BRFR have a four-queue structure. When the stored address is read in a PC trace, the read is performed from the head of the queue. Reads should be performed in the order BRFR, BRSR, BRDR.
Page 270 Section 6 User Break Controller (UBC) B. Register settings: BARA = H'00027128 / BAMRA = H'00000000 / BBRA = H'005A BARB = H'00031415 / BAMRB = H'00000000 / BBRB = H'0054 BARC = H'00037226 / BAMRC = H'00000000 / BBRC = H'0056 BDRC = H'00000000 / BDMRC = H'00000000 BARD = H'0003722E / BAMRD = H'00000000 / BBRD = H'0056 BDRD = H'00000000 / BDMRD = H'00000000...
Page 271 Section 6 User Break Controller (UBC) Channels A and B independent, channel C → channel D sequential mode Set conditions: Channel A: Not used Channel B: Not used Channel C: Address: H'00037226; address mask: H'00000000 Data: H'00000000; data mask: H'00000000 Bus cycle: CPU, instruction fetch (pre-execution), write, word Channel D: Address: H'0003722E;...
Page 272 Section 6 User Break Controller (UBC) After the instruction at address H'0000500 is executed, and the instruction at address H'00000A00 is executed five times, a user break interrupt is generated after the instruction at address H'00001000 has been executed nine times, but before it is executed a tenth time. CPU Data Access Cycle Break Condition Settings Register settings: BARA = H'00123456 / BAMRA = H'00000000 / BBRA = H'0064 BARB = H'01000000 / BAMRB = H'00000000 / BBRB = H'0066...
Page 273: Usage Notes
Section 6 User Break Controller (UBC) DMA Data Access Cycle Break Condition Settings Register settings: BARA = H'00314156 / BAMRA = H'00000000 / BBRA = H'0094 BBRB = H'0000 BBRC = H'0000 BARD = H'00055555 / BAMRD = H'00000000 / BBRD = H'00A9 BDRD = H'00007878 / BDMRD = H'00000F0F BRCR = H'00000008 Set conditions:...
Page 274 Section 6 User Break Controller (UBC) 3. When changing a register setting, the written value normally becomes effective in three cycles. In an on-chip memory fetch, two instructions are fetched simultaneously. If the fetch of the second instruction has been set as a break condition, even if the break condition is changed by modifying the relevant UBC registers immediately after the fetch of the first instruction, a user break interrupt will still be generated prior to the second instruction.
Page 275: Section 7 Bus State Controller (Bsc)
Section 7 Bus State Controller (BSC) Section 7 Bus State Controller (BSC) Overview The bus state controller (BSC) manages the address spaces and outputs control signals to allow optimum memory accesses to the five spaces. This enables memories like DRAM, and SDRAM, and peripheral chips, to be linked directly.
Page 276 Section 7 Bus State Controller (BSC)  Selection of burst read, single write mode or burst read, burst write mode  Bank active mode • Bus arbitration  All resources are shared with the CPU, and use of the bus is granted on reception of a bus release request from off-chip.
Page 277: Block Diagram
Section 7 Bus State Controller (BSC) 7.1.2 Block Diagram Figure 7.1 shows a block diagram of the BSC. interface WCR1 Wait WCR2 control WAIT unit WCR3 BCR1 Area CS4–CS0 control BCR2 unit BCR3 STATS1, 0 RTCSR RD/WR Memory WE3–WE0 control RTCNT unit IVECF...
Page 278: Pin Configuration
Section 7 Bus State Controller (BSC) 7.1.3 Pin Configuration Table 7.1 shows the BSC pin configuration. Table 7.1 Pin Configuration With Bus Signal Released Description A24–A0 Hi-Z Address bus. 32 Mbytes of memory space can be specified with 25 bits D31–D0 Hi-Z 32-bit data bus.
Page 279 Section 7 Bus State Controller (BSC) With Bus Signal Released Description DREQ1 DMA request 1 DACK1 DMA acknowledge 1 REFOUT Refresh execution request output when bus is released DQMUU/ Hi-Z When synchronous DRAM is used, connected to DQM pin for the most significant byte (D31–D24).
Page 280: Register Configuration
Section 7 Bus State Controller (BSC) 7.1.4 Register Configuration The BSC has ten registers. These registers are used to control wait states, bus width, interfaces with memories like DRAM, synchronous DRAM, and burst ROM, and DRAM and synchronous DRAM refreshing. The register configurations are shown in table 7.2. The size of the registers themselves is 16 bits.
Page 281: Address Map
Section 7 Bus State Controller (BSC) 7.1.5 Address Map The address map, which has a memory space of 320 Mbytes, is divided into five spaces. The types and data width of devices that can be connected are specified for each space. The overall space address map is shown in table 7.3.
Page 282 Section 7 Bus State Controller (BSC) Address Space Memory Size H'24000000–H'25FFFFFF CS2 space, cache-through Ordinary space or 32 Mbytes synchronous DRAM * area H'26000000–H'27FFFFFF CS3 space, cache-through Ordinary space, 32 Mbytes synchronous DRAM * area , or DRAM H'28000000–H'29FFFFFF CS4 space, cache-through Ordinary space (I/O 32 Mbytes area...
Page 283: Register Descriptions
Section 7 Bus State Controller (BSC) Register Descriptions 7.2.1 Bus Control Register 1 (BCR1) Bit: — A4LW1 A4LW0 A2EN — AHLW1 AHLW0 DIAN Initial value: R/W: Bit: A1LW1 A1LW0 A0LW1 A0LW0 A4EN DRAM2 DRAM1 DRAM0 DIAN Initial value: R/W: Initialize the ENDIAN, BSTROM, PSHR, and DRAM2–DRAM0 bits after a power-on reset, and do not change their values thereafter.
Page 284 Section 7 Bus State Controller (BSC) Bit 11—Area 0 Burst ROM Enable (BSTROM) Bit 11: BSTROM Description Area 0 is accessed normally (Initial value) Area 0 is accessed as burst ROM Bit 10—Reserved: This bit is always read as 0. The write value should always be 0. Bits 9 and 8—Long Wait Specification for Areas 2 and 3 (AHLW1, AHLW0): When the basic memory interface setting is made for CS2 and CS3, from 3 to 14 wait cycles are inserted in CS2 or CS3 accesses when the bits specifying the respective area waits in the wait control bits (W21,...
Page 285 Section 7 Bus State Controller (BSC) Bits 2 to 0—Enable for DRAM and Other Memory (DRAM2–DRAM0) DRAM2 DRAM1 DRAM0 Description CS2 and CS3 are ordinary spaces (Initial value) CS2 is ordinary space; CS3 is synchronous DRAM space CS2 is ordinary space; CS3 is DRAM space Reserved (do not set) CS2 is synchronous DRAM space, CS3 is ordinary space CS2 and CS3 are synchronous DRAM spaces...
Page 286: Bus Control Register 2 (Bcr2)
Section 7 Bus State Controller (BSC) 7.2.2 Bus Control Register 2 (BCR2) Bit: — — — — — — A4SZ1 A4SZ0 Initial value: R/W: Bit: A3SZ1 A3SZ0 A2SZ1 A2SZ0 A1SZ1 A1SZ0 — — Initial value: R/W: Initialize BCR2 after a power-on reset and do not write to it thereafter. When writing to it, write the same values as those the bits are initialized to.
Page 287: Bus Control Register 3 (Bcr3)
Section 7 Bus State Controller (BSC) Bits 5 and 4—Bus Size Specification for Area 2 (CS2) (A2SZ1, A2SZ0): Effective only when ordinary space is set. Bit 5: A2SZ1 Bit 4: A2SZ0 Description Reserved (do not set) Byte (8-bit) size Word (16-bit) size Longword (32-bit) size (Initial value) Bits 3 and 2—Bus Size Specification for Area 1 (CS1) (A1SZ1, A1SZ0)
Page 288 Section 7 Bus State Controller (BSC) Bits 11 to 8—Long Wait Specification for Areas 0 to 4 (AnLW2): When the basic memory interface setting is made for CS n, from 3 to 14 wait cycles are inserted in CS n accesses, according to the combination with the long wait specification bits (AnLW1 and AnLW0) in BCR1, when the bits specifying the wait in the wait control register are set as long wait (i.e., are set to 11).
Page 289: Wait Control Register 1 (Wcr1)
Section 7 Bus State Controller (BSC) Bit 0—Synchronous DRAM Burst Write Specification (BWE): Enables burst write mode to be specified when synchronous DRAM is specified for CS2 or CS3 space. Bit 0: BWE Description Single write mode (Initial value) Burst write mode 7.2.4 Wait Control Register 1 (WCR1) Bit:...
Page 290 Section 7 Bus State Controller (BSC) Bits 7 to 0—Wait Control for Areas 3 to 0 (W31–W00) • When the CSn space is set as ordinary space, the number of CSn space waits can be specified with Wn1 and Wn0. W31, W21, W30, W20, W11, W01...
Page 291: Wait Control Register 2 (Wcr2)
Section 7 Bus State Controller (BSC) 7.2.5 Wait Control Register 2 (WCR2) Bit: A4WD1 A4WD0 — A4WM A3WM A2WM A1WM A0WM Initial value: R/W: Bit: — — — — IW41 IW40 Initial value: R/W: Bits 15 and 14—Number of External Waits Specification for Area 4 (A4WD1, A4WD0): These bits specify the number of cycles between acceptance of CS4 space external wait negation and RD or WEn negation.
Page 292 Section 7 Bus State Controller (BSC) A4WM A3WM A2WM A1WM A0WM Description External wait input ignored External wait input enabled External wait input enabled External wait input enabled (Initial value) Don’t care Don’t care External wait input ignored Bits 7 to 4—Reserved bits: These bits are always read as 0. The write value should always be 0. Bits 3 and 2—Idles between Cycles for Area 4 (IW41, IW40): These bits specify idle cycles inserted between cycles in CS4 in the same way as for CS 0 to 3.
Page 293: Wait Control Register 3 (Wcr3)
Section 7 Bus State Controller (BSC) 7.2.6 Wait Control Register 3 (WCR3) Bit: — — A4SW2 A4SW1 A4SW0 — A4HW1 A4HW0 Initial value: R/W: Bit: A3SHW1 A3SHW0 A2SHW1 A2SHW0 A1SHW1 A1SHW0 A0SHW1 A0SHW0 Initial value: R/W: Bits 15 and 14—Reserved bits: These bits are always read as 0. The write value should always be Bits 13 to 11—CS4 Address/CS4 to RD/WEn Assertion (A4SW2–A4SW0): These bits specify the number of cycles from address/CS4 output to RD/WEn assertion for the CS4 space.
Page 294: Individual Memory Control Register (Mcr)
Section 7 Bus State Controller (BSC) Bits 7 to 0—Area 3 to 0 CSn Assert Period Extension (A3SHW1–A0SHW0): These bits specify the number of cycles from address/CSn output to RD/WEn assertion and from RD/WEn negation to address/CSn hold for areas 3 to 0. A3SHW1 A3SHW0 A2SHW1...
Page 295 Section 7 Bus State Controller (BSC) • For DRAM interface Bit 1: TRP1 Bit 15: TRP0 Description 1 cycle (Initial value) 2 cycles Reserved (do not set) Reserved (do not set) • For Synchronous DRAM interface Bit 1: TRP1 Bit 15: TRP0 Description 1 cycle (Initial value)
Page 296 Section 7 Bus State Controller (BSC) Bits 12 and 11—CAS-Before-RAS Refresh RAS Assert Time (TRAS1, TRAS0): These bits specify the RAS assertion width when DRAM is connected. Bit 12: TRAS1 Bit 11: TRAS0 Description 2 cycles (Initial value) 3 cycles 4 cycles 5 cycles After an auto-refresh command is issued, a bank active command is not issued for TRAS cycles,...
Page 297 Section 7 Bus State Controller (BSC) Bit 9—Bank Active Mode (RASD) Bit 9: RASD Description For DRAM, RAS is negated after access ends (normal operation) For synchronous DRAM, a read or write is performed using auto-precharge mode. The next access always starts with a bank active command (Initial value) For DRAM, after access ends RAS down mode is entered in which RAS is left asserted.
Page 298 Section 7 Bus State Controller (BSC) • For synchronous DRAM interface Bit 7: AMX2 Bit 5: AMX1 Bit 4: AMX0 Description 16-Mbit DRAM (1 M × 16 bits), 64-Mbit DRAM (2 M × 32 bits) * 16-Mbit DRAM (2 M × 8 bits) * 16-Mbit DRAM (4 M ×...
Page 299 Section 7 Bus State Controller (BSC) 128 Mbit (1 Mword × 32 bit × 4 Bank) Chip synchronous DRAM CKIO RD/WR I/O31 I/O0 DQMUU/WE3 DQMUU DQMUL/WE2 DQMUL DQMLU/WE1 DQMLU DQMLL/WE0 DQMLL Figure 7.2 128 Mbit Synchronous DRAM (4 Mword × 32 bit) Connection Example Rev.
Page 300 Section 7 Bus State Controller (BSC) 128 Mbit (2 Mword × 16-bit × 4 bank) Chip synchronous DRAM CKIO RD/WR I/O15 I/O0 DQMUU/WE3 DQMU DQMUL/WE2 DQML DQMLU/WE1 DQMLL/WE0 I/O15 I/O0 DQMU DQML Figure 7.3 128 Mbit Synchronous DRAM (8 Mword × 16 bit) Connection Example Rev.
Page 301 Section 7 Bus State Controller (BSC) 256 Mbit (2 Mword × 32-bit × 4 Bank) Chip synchronous DRAM CKIO RD/WR I/O31 I/O0 DQMUU/WE3 DQMUU DQMUL/WE2 DQMUL DQMLU/WE1 DQMLU DQMLL/WE0 DQMLL Figure 7.4 256 Mbit Synchronous DRAM (8 Mword × 32 bit) Connection Example Bit 6—Memory Data Size (SZ): For synchronous DRAM and DRAM space, the data bus width of BCR2 is ignored in favor of the specification of this bit.
Page 302: Refresh Timer Control/Status Register (Rtcsr)
Section 7 Bus State Controller (BSC) is 0, a CAS-before-RAS refresh or auto-refresh is performed at the interval set in the 8-bit interval timer. When a refresh request occurs during an external area access, the refresh is performed after the access cycle is completed. When set for self-refresh, self-refresh mode is entered immediately unless the chip is in the middle of a synchronous DRAM area access, in which case self-refresh mode is entered when the access ends.
Page 303 Section 7 Bus State Controller (BSC) Bit 6—Compare Match Interrupt Enable (CMIE): Enables or disables an interrupt request caused by the CMF bit of RTCSR when CMF is set to 1. Bit 6: CMIE Description Interrupt request caused by CMF is disabled (Initial value) Interrupt request caused by CMF is enabled Bits 5 to 3—Clock Select Bits (CKS2–CKS0)
Page 304: Refresh Timer Counter (Rtcnt)
Section 7 Bus State Controller (BSC) 7.2.9 Refresh Timer Counter (RTCNT) Bit: — — — — — — — — Initial value: R/W: Bit: Initial value: R/W: The 8-bit counter RTCNT counts up with input clocks. The clock select bit of RTCSR selects an input clock.
Page 305: Access Size And Data Alignment
Section 7 Bus State Controller (BSC) When the CMIE bit in RTCSR is set to 1, an interrupt request is sent to the controller by this match signal. The interrupt request is output continuously until the CMF bit in RTCSR is cleared. When the CMF bit clears, it only affects the interrupt;...
Page 306: Connection To Little-Endian Devices
7.8, 7.9, and 7.10. When sharing memory or the like with a little-endian bus master, the SH7616 connects D31–D24 to the least significant byte (LSB) of the other bus master and D7–D0 to the most significant byte (MSB), when the bus width is 32 bits. When the width is Rev.
Page 307 Section 7 Bus State Controller (BSC) 16 bits, the SH7616 connects D15–D8 to the least significant byte of the other bus master and D7– D0 to the most significant byte. Only data conversion is supported by this function. For this reason, be careful not to place program code or constants in the CS2, CS4 space.
Page 308: Accessing Ordinary Space
Section 7 Bus State Controller (BSC) 8-bit external device (little-endian) A24–A0 Data input/output pin 000000 Byte read/write of address 0 000001 Byte read/write of address 1 000002 Byte read/write of address 2 000003 Byte read/write of address 3 000000 Word read/write of address 0 000001 000002 Word read/write of address 2...
Page 309 Section 7 Bus State Controller (BSC) CKIO A24–A0 RD/WR Read D31–D0 Write D31–D0 DACKn* Note: * DACKn waveform when active-low is specified. Figure 7.11 Basic Timing of Ordinary Space Access When making a word or longword access with an 8-bit bus width, or a longword access with a 16- bit bus width, the bus state controller performs multiple accesses.
Page 310 Section 7 Bus State Controller (BSC) CKIO A24–A0 RD/WR Read D15–D0 Write D15–D0 DACKn* Note: * DACKn waveform when active-low is specified. Figure 7.12 Timing of Longword Access in Ordinary Space Using 16-Bit Bus Width (Clock Ratio Iφ φ φ φ : Eφ φ φ φ = 1 : 1) Figure 7.13 shows an example of 32-bit data width SRAM connection, figure 7.14 an example of 16-bit data width SRAM connection, and figure 7.15 an example of 8-bit data width SRAM connection.
Page 311 Section 7 Bus State Controller (BSC) 128 k × 8-bit Chip SRAM I/O7 I/O0 DQMUU/WE3 DQMUL/WE2 DQMLU/WE1 I/O7 I/O0 DQMLL/WE0 I/O7 I/O0 I/O7 I/O0 Figure 7.13 Example of 32-Bit Data Width SRAM Connection Rev. 2.00 Mar 09, 2006 page 285 of 906 REJ09B0292-0200...
Page 312 Section 7 Bus State Controller (BSC) 128 k × 8-bit Chip SRAM I/O7 I/O0 DQMLU/WE1 DQMLL/WE0 I/O7 I/O0 Figure 7.14 Example of 16-Bit Data Width SRAM Connection 128 k × 8-bit Chip SRAM I/O7 I/O0 DQMLL/WE0 Figure 7.15 Example of 8-Bit Data Width SRAM Connection Rev.
Page 313: Wait State Control
Section 7 Bus State Controller (BSC) 7.4.2 Wait State Control The number of wait states inserted into ordinary space access states can be controlled using the WCR1, WCR2, BCR1 and BCR3 register settings. When the Wn1 and Wn0 wait specification bits in WCR1, WCR2 for the given CS space are 01 or 10, software waits are inserted according to the wait specification.
Page 314 Section 7 Bus State Controller (BSC) Table 7.5 CSn Spaces and Tw Specification Bits BCR3 BCR1 WCR1 WCR2 A0LW2 A0LW1 A0LW0 — — 0–14 A1LW2 A1LW1 A2LW0 — — 0–14 AHLW2 AHLW1 AHLW0 — — 0–14 AHLW2 AHLW1 AHLW0 — —...
Page 315 Section 7 Bus State Controller (BSC) Wait states from WAIT signal input CKIO A24–A0 RD/WR Read D31–D0 Write D31–D0 WAIT DACKn* Note: * DACKn waveform when active-low is specified. Figure 7.17 Wait State Timing of Ordinary Space Access (Wait States from WAIT WAIT WAIT WAIT Signal)
Page 316 Section 7 Bus State Controller (BSC) For the CS0–CS3 spaces, CSn, RD, and WEn are negated for one cycle after negation of the external wait signal is accepted, as shown in figure 7.17. For the CS4 space, the number of cycles before CSn, RD, and WEn are negated after acceptance of external wait negation can be set as 1, 2, or 4 by means of bits A4WD1 and A4WD0 in WCR2.
Page 317: Cs Assertion Period Extension
Section 7 Bus State Controller (BSC) CS Assertion Period Extension 7.4.3 Idle cycles can be inserted to prevent extension of the RD or WEn assertion period beyond the length of the CSn assertion period by setting control bits in WCR3. This allows for flexible interfacing to external circuit.
Page 318: Synchronous Dram Interface
Section 7 Bus State Controller (BSC) For the CS0–CS4 spaces, For spaces CS0—CS4, Th and Tf can be set as follows. WCR3 CS0—3 0—2 0—2 AnSW1, AnSW0 (Th = Tf) n =0—3 0—7 0—5 Th: A4SW2—0 Tf: A4HW1—0 Synchronous DRAM Interface 7.5.1 Synchronous DRAM Direct Connection Seven kinds of synchronous DRAM can be connected: 2-Mbit (128 k ×...
Page 319 Section 7 Bus State Controller (BSC) Bytes are specified using DQMUU, DQMUL, DQMLU, and DQMLL. The read/write is performed on the byte whose DQM is low. For 32-bit data, DQMUU specifies 4n address access and DQMLL specifies 4n + 3 address access. For 16-bit data, only DQMLU and DQMLL are used.
Page 320: Address Multiplexing
(A0) specifies word address. The A0 pin of the synchronous DRAM is thus connected to the A1 pin of the SH7616, the rest of the connection proceeding in the same order, beginning with the A1 pin to the A2 pin.
Page 321 Section 7 Bus State Controller (BSC) Table 7.6 SZ and AMX Bits and Address Multiplex Output Setting External Address Pins Output SZ AMX2 AMX1 AMX0 Timing A1–A8 L/H * A21 * Column A1–A8 address A21 * A9–A16 A17 address L/H * A22 * Column A1–A8...
Page 322: Burst Reads
Section 7 Bus State Controller (BSC) Setting External Address Pins Output SZ AMX2 AMX1 AMX0 Timing A1–A8 LH * A21 * A22 * Column A1–A8 address A21 * A22 * A9–A16 A17 address L/H * A18 * Column A1–A8 address A18 * A9–A16 A17 address...
Page 323 Section 7 Bus State Controller (BSC) output cycle Tc and the initial read data fetch cycle Td1 can be specified between 1 cycle and 4 cycles using the W21/W20 and W31/W30 bits in WCR1. The number of cycles at this time corresponds to the number of CAS latency cycles of the synchronous DRAM.
Page 324 Section 7 Bus State Controller (BSC) CKIO A24–A11 A9–A1 CS2 or CS3 RD/WR DQMxx D31–D0 DACKn* Note: * DACKn waveform when active-low is specified. Figure 7.22 (b) Basic Burst Read Timing (Auto-Precharge) Iφ φ φ φ : Eφ φ φ φ = 1 : 1 Rev.
Page 325 Section 7 Bus State Controller (BSC) CKIO A24–A11 A9–A1 CS2 or CS3 RD/WR DQMxx D31–D0 DACKn* Note: * DACKn waveform when active-low is specified. Figure 7.23 (a) Burst Read Wait Specification Timing (Auto-Precharge) Iφ φ φ φ : Eφ φ φ φ other than 1 : 1 Rev.
Page 326 Section 7 Bus State Controller (BSC) CKIO A24–A11 A9–A1 CS2 or CS3 RD/WR DQMxx D31–D0 DACKn* Note: * DACKn waveform when active-low is specified. Figure 7.23 (b) Burst Read Wait Specification Timing (Auto-Precharge) Iφ φ φ φ : Eφ φ φ φ = 1 : 1 Rev.
Page 327: Single Reads
Section 7 Bus State Controller (BSC) 7.5.4 Single Reads When a cache area is accessed and there is a cache miss, the cache fill cycle is performed in 16- byte units. This means that all the data read in the burst read is valid. On the other hand, when a cache-through area is accessed the required data is a maximum length of 32 bits, and the remaining 12 bytes are wasted.
Page 328 Section 7 Bus State Controller (BSC) CKIO A24–A11 A9–A1 CS2 or CS3 RD/WR DQMxx D31–D0 DACKn* Note: * DACKn waveform when active-low is specified. Figure 7.24 (a) Single Read Timing (Auto-Precharge) Iφ φ φ φ : Eφ φ φ φ other than 1 : 1 Rev.
Page 329: Single Writes
Section 7 Bus State Controller (BSC) CKIO A24–A11 A9–A1 CS2 or CS3 RD/WR DQMxx D31–D0 DACKn* Note: * DACKn waveform when active-low is specified. Figure 7.24 (b) Single Read Timing (Auto-Precharge) Iφ φ φ φ : Eφ φ φ φ = 1 : 1 7.5.5 Single Writes Synchronous DRAM writes are executed as single writes or burst writes according to the...
Page 330: Burst Write Mode
Section 7 Bus State Controller (BSC) Trwl CKIO A24–A11 A9–A1 CS2 or CS3 RD/WR DQMxx D31–D0 DACKn* Note: * DACKn waveform when active-low is specified. Figure 7.25 Basic Single Write Cycle Timing (Auto-Precharge) 7.5.6 Burst Write Mode Burst write mode can be selected by setting the BWE bit to 1 in BCR3. The basic timing charts for burst write access is shown in figure 7.26 (a) and (b).
Page 331 Section 7 Bus State Controller (BSC) Tap cycles can be set respectively in MCR by bits TRWL1 and TRWL0, and bits TRP1 and TRP0. When a single write is performed in burst write mode, the synchronous DRAM setting is for a burst length of 4.
Page 332: Bank Active Function
Section 7 Bus State Controller (BSC) Trwl CKIO A24–A11 A9–A1 CS2 or CS3 RD/WR DQMxx D31–D0 DACKn* Note: * DACKn waveform when active-low is specified. Figure 7.26 (b) Basic Burst Write Timing (Auto-Precharge) Iφ φ φ φ : Eφ φ φ φ = 1 : 1 7.5.7 Bank Active Function A synchronous DRAM bank function is used to support high-speed accesses of the same row...
Page 333 Section 7 Bus State Controller (BSC) addresses, the precharge is performed after the access request occurs, so the access time is longer. When writing, performing an auto-precharge means that no command can be called for t cycles after a WRITA command is called. When the bank active mode is used, READ or WRIT commands can be issued consecutively if the row address is the same.
Page 334 Section 7 Bus State Controller (BSC) after this is detected. Both banks will become inactive even in the bank active mode after the refresh cycle ends or after the bus is released by bus arbitration. CKIO A24–A11 A9–A1 RD/WR DQMxx D31–D0 DACKn* Note: * DACKn waveform when active-low is specified.
Page 335 Section 7 Bus State Controller (BSC) CKIO A24–A11 A9–A1 RD/WR DQMxx D31–D0 DACKn* Note: * DACKn waveform when active-low is specified. Figure 7.27 (b) Burst Read Timing (No Precharge) Iφ φ φ φ : Eφ φ φ φ = 1 : 1 Rev.
Page 336 Section 7 Bus State Controller (BSC) Tnop CKIO A24–A11 A9–A1 RD/WR DQMxx D31–D0 DACKn* Note: * DACKn waveform when active-low is specified. Figure 7.28 (a) Burst Read Timing (Bank Active, Same Row Address) Iφ φ φ φ : Eφ φ φ φ other than 1 : 1 Rev.
Page 337 Section 7 Bus State Controller (BSC) Tnop CKIO A24–A11 A9–A1 RD/WR DQMxx D31–D0 DACKn* Note: * DACKn waveform when active-low is specified. Figure 7.28 (b) Burst Read Timing (Bank Active, Same Row Address) Iφ φ φ φ : Eφ φ φ φ = 1 : 1 Rev.
Page 338 Section 7 Bus State Controller (BSC) CKIO A24–A11 A9–A1 RD/WR DQMxx D31–D0 DACKn* Note: * DACKn waveform when active-low is specified. Figure 7.29 (a) Burst Read Timing (Bank Active, Different Row Addresses) Iφ φ φ φ : Eφ φ φ φ other than 1 : 1 Rev.
Page 339 Section 7 Bus State Controller (BSC) CKIO A24 – A11 A9 – A1 RD/WR DQMxx D31 – D0 DACKn* Note: * DACKn waveform when active-low is specified. Figure 7.29 (b) Burst Read Timing (Bank Active, Different Row Addresses) Iφ φ φ φ : Eφ φ φ φ = 1 : 1 Rev.
Page 340 Section 7 Bus State Controller (BSC) CKIO A24–A11 A9–A1 RD/WR DQMxx D31–D0 DACKn* Note: * DACKn waveform when active-low is specified. Figure 7.30 Single Write Mode Timing (No Precharge) Rev. 2.00 Mar 09, 2006 page 314 of 906 REJ09B0292-0200...
Page 341 Section 7 Bus State Controller (BSC) CKIO A24–A11 A9–A1 RD/WR DQMxx D31–D0 DACKn* Note: * DACKn waveform when active-low is specified. Figure 7.31 Single Write Mode Timing (Bank Active, Same Row Address) Rev. 2.00 Mar 09, 2006 page 315 of 906 REJ09B0292-0200...
Page 342 Section 7 Bus State Controller (BSC) CKIO A24–A11 A9–A1 RD/WR DQMxx D31–D0 DACKn* Note: * DACKn waveform when active-low is specified. Figure 7.32 Single Write Mode Timing (Bank Active, Different Row Addresses) Rev. 2.00 Mar 09, 2006 page 316 of 906 REJ09B0292-0200...
Page 343: Refreshes
Section 7 Bus State Controller (BSC) 7.5.8 Refreshes The bus state controller is equipped with a function to control refreshes of synchronous DRAM. Auto-refreshes can be performed by setting the RMODE bit to 0 and the RFSH bit to 1 in MCR. Consecutive refreshes can also be generated by setting the RRC2–RRC0 bits in RTCSR.
Page 344 Section 7 Bus State Controller (BSC) CKIO CS2 or CS3 RD/WR DQMxx Figure 7.33 Auto-Refresh Timing Self-Refreshes: The self-refresh mode is a type of standby mode that produces refresh timing and refresh addresses within the synchronous DRAM. It is started up by setting the RMODE and RFSH bits to 1.
Page 345 In the SH7616, the REFOUT pin is provided to send a signal requesting the bus right during the wait for refreshing to be executed. REFOUT is asserted until the bus is acquired.
Page 346: Overlap Between Auto Precharge Cycle (Tap) And Next Access
Section 7 Bus State Controller (BSC) 7.5.9 Overlap Between Auto Precharge Cycle (Tap) and Next Access If the CPU and DMAC or E-DMAC are accessed sequentially and the first access is to SDRAM and also in the auto precharge mode, the auto precharge cycle (Tap) of the first access may overlap the second access if the second access is to a different memory space or to a different bank of the same SDRAM.
Page 347: Power-On Sequence
Section 7 Bus State Controller (BSC) 7.5.10 Power-On Sequence To use synchronous DRAM, the mode must first be set after the power is turned on. To properly initialize the synchronous DRAM, the synchronous DRAM mode register must be written to after the registers of the bus state controller have first been set.
Page 348 MCR setting. After writing to the synchronous DRAM mode register, perform a dummy read to each synchronous DRAM bank before starting normal access. This will initialize the SH7616's internal address comparator.
Page 349: 64 Mbit Synchronous Dram (2 Mword × × × × 32-Bit) Connection
64 Mbit Synchronous DRAM (2 Mword × × × × 32-bit) Connection 7.5.11 64 Mbit Synchronous DRAM (× × × × 32-bit) Connection Example: Figure 7.37 shows an example connection between the SH7616 and 64 Mbit synchronous DRAM (× 32-bit). 2 Mword × 32-bit SDRAM...
Page 350: Dram Interface
Section 7 Bus State Controller (BSC) DRAM Interface 7.6.1 DRAM Direct Connection When the DRAM and other memory enable bits (DRAM2–DRAM0) in BCR1 are set to 010, the CS3 space becomes DRAM space, and a DRAM interface function can be used to directly connect DRAM.
Page 351: Address Multiplexing
Section 7 Bus State Controller (BSC) 256 k × 16-bit Chip DRAM RD/WR I/O15 I/O0 CAS1 UCAS CAS0 LCAS Figure 7.39 Example of DRAM Connection (16-Bit Data Width) 7.6.2 Address Multiplexing When the CS3 space is set to DRAM, addresses are always multiplexed. This allows DRAMs that require multiplexing of row and column addresses to be connected directly without additional address multiplexing circuits.
Page 352: Basic Timing
Section 7 Bus State Controller (BSC) 7.6.3 Basic Timing The basic timing of a DRAM access is 3 cycles. Figure 7.40 shows the basic DRAM access timing. Tp is the precharge cycle, Tr is the RAS assert cycle, Tc1 is the CAS assert cycle, and Tc2 is the read data fetch cycle.
Page 353: Wait State Control
Section 7 Bus State Controller (BSC) 7.6.4 Wait State Control When the clock frequency is raised, 1 cycle may not always be sufficient for all states to end, as in basic access. Setting bits in WCR1, WCR2 and MCR enables the state to be lengthened. Figure 7.41 shows an example of lengthening a state using settings.
Page 354 Section 7 Bus State Controller (BSC) CKIO A24–A16 A15–A1 CASn RD/WR Read D31–D0 RD/WR Write D31–D0 DACKn * Note: * DACKn waveform when active-low is specified Figure 7.41 Wait State Timing Rev. 2.00 Mar 09, 2006 page 328 of 906 REJ09B0292-0200...
Page 355: Burst Access
Section 7 Bus State Controller (BSC) CKIO A24–A16 A15–A1 CASn RD/WR Read D31–D0 RD/WR Write D31–D0 DACKn * WAIT Note: * DACKn waveform when active-low is specified Figure 7.42 External Wait State Timing 7.6.5 Burst Access In addition to the ordinary mode of DRAM access, in which row addresses are output at every access and data is then accessed, DRAM also has a high-speed page mode for use when continuously accessing the same row that enables fast access of data by changing only the column address after the row address is output.
Page 356 BE bit in MCR is set to 1, setting the MCR’s RASD bit (which specifies RAS down mode) to 1 places the SH7616 in RAS down mode, which leaves the RAS signal asserted. The access timing in RAS down mode is shown in figures 7.44 and 7.45. When RAS down mode is used, the refresh cycle must be less than the maximum DRAM RAS assert time tRAS when the refresh cycle is longer than the tRAS maximum.
Page 357 Section 7 Bus State Controller (BSC) CKIO A24–A14 A13–A1 CASn RD/WR Read D31–D0 RD/WR Write D31–D0 DACKn* Note: * DACKn waveform when active-low is specified Figure 7.44 RAS RAS Down Mode Same Row Access Timing Rev. 2.00 Mar 09, 2006 page 331 of 906 REJ09B0292-0200...
Page 358: Edo Mode
Section 7 Bus State Controller (BSC) CKIO A24–A16 A15–A1 CASn RD/WR Read D31–D0 RD/WR Write D31–D0 DACKn * Note: * DACKn waveform when active-low is specified Figure 7.45 RAS RAS Down Mode Different Row Access Timing 7.6.6 EDO Mode In addition to the kind of DRAM in which data is output to the data bus only while the CASn signal is asserted in a data read cycle, there is another kind provided with an EDO mode in which, while both RAS and OE are asserted, once the CASn signal is asserted data is output to the data bus until CASn is next asserted, even though CASn is negated during this time.
Page 359 The EDO mode bit (EDO) in MCR allows selection of ordinary access/high-speed page mode burst access or ordinary access/burst access using EDO mode. Since OE control is performed in EDO mode DRAM access, the CAS and OE pins of the SH7616 must be connected to the OE pin of the DRAM.
Page 360 Section 7 Bus State Controller (BSC) 256 k × 16-bit Chip DRAM RD/WR I/O15 I/O0 CAS1 UCAS CAS0 LCAS CAS/OE Figure 7.47 Example of EDO DRAM Connection (16-Bit Data Width) Rev. 2.00 Mar 09, 2006 page 334 of 906 REJ09B0292-0200...
Page 361 Section 7 Bus State Controller (BSC) (Tpc) CKIO A24–A16 Row address A15–A1 Row address Column address RD/WR CASn D15–D0 Read CAS/OE D15–D0 Write CAS/OE High level DACKn * Note: * DACKn waveform when active-low is specified Figure 7.48 DRAM EDO Mode Ordinary Access Timing Rev.
Page 362: Dram Single Transfer
Section 7 Bus State Controller (BSC) (Tpc) CKIO A24–A16 Row address A15–A1 Column address Column address Column address Column address address RD/WR CASn D15–D0 Read CAS/OE D15–D0 Write High CAS/OE DACKn * Note: * DACKn waveform when active-low is specified Figure 7.49 DRAM EDO Mode Burst Access Timing 7.6.7 DRAM Single Transfer...
Page 363: Refreshing
Section 7 Bus State Controller (BSC) Tdsww CKIO A24–A16 A15–A1 Low level CASn RD/WR D31–D0 DACKn * Note: * DACKn waveform when active-low is specified Figure 7.50 DMA Single Transfer Mode Write Cycle Timing RAS Down Mode, Same Row Address) (RAS 7.6.8 Refreshing...
Page 364 Section 7 Bus State Controller (BSC) specification for the DRAM used. First make the settings for RTCOR, RTCNT, and the RMODE and RFSH bits in MCR, then make the CKS2–CKS0 and RRC2–RRC0 settings in RTCSR. When the clock is selected by CKS2–CKS0, RTCNT starts counting up from the value at that time. The RTCNT value is constantly compared with the RTCOR value, and when the two values match, a refresh request is generated and the number of CAS-before-RAS refreshes set in bits RRC2–RRC0 are performed.
Page 365: Power-On Sequence
Section 7 Bus State Controller (BSC) After self-refreshing has been set, the self-refresh state continues even if the chip standby state is entered using the chip’s standby function. The self-refresh state is also maintained even after recovery from standby mode by means of NMI input. In the case of a power-on reset, the bus state controller’s registers are initialized, and therefore the self-refresh state is cleared.
Page 366 Section 7 Bus State Controller (BSC) accesses are performed; when connecting to a 16-bit width ROM, a maximum of 2 consecutive accesses are performed. Figure 7.53 shows the relationship between data width and access size. For cache filling and DMAC 16-byte transfers, longword accesses are repeated 4 times. When one or more wait states are set for a burst ROM access, the WAIT pin is sampled.
Page 367 Section 7 Bus State Controller (BSC) CKIO A24–A0 RD/WR D31–D0 DACKn* Note: * DACKn waveform when active-low is specified. Figure 7.54 Burst ROM Nibble Access (2 Wait States) Rev. 2.00 Mar 09, 2006 page 341 of 906 REJ09B0292-0200...
Page 368 Section 7 Bus State Controller (BSC) CKIO A24–A0 RD/WR D31–D0 DACKn* Note: * DACKn waveform when active-low is specified. Figure 7.55 Burst ROM Nibble Access (No Wait States) Rev. 2.00 Mar 09, 2006 page 342 of 906 REJ09B0292-0200...
Page 369: Idles Between Cycles
Section 7 Bus State Controller (BSC) Idles between Cycles Because operating frequencies have become high, when a read from a slow device is completed, data buffers may not go off in time to prevent data conflicts with the next access. This lowers device reliability and causes errors.
Page 370 Section 7 Bus State Controller (BSC) Twait Twait CKIO A24–A0 RD/WR D31–D0 CSm space read CSn space read CSn space write Specification of waits Specification of waits between CSm accesses between CSn accesses (reading different spaces) (read followed by write) Figure 7.56 Idles between Cycles Rev.
Page 371: Bus Arbitration
Section 7 Bus State Controller (BSC) Bus Arbitration The chip has a bus arbitration function that, when a bus release request is received from an external device, releases the bus to that device after the bus cycle being executed is completed. The chip keeps the bus under normal conditions and permits other devices to use the bus by releasing it when they request its use.
Page 372 Section 7 Bus State Controller (BSC) bus cycles produced by a data width smaller than the access size, such as a longword access to an 8-bit data width memory. Bus arbitration is performed between external vector fetch, PC save, and SR save cycles during interrupt handling, which are all independent accesses.
Page 373 Section 7 Bus State Controller (BSC) Figure 7.57 (a) Bus Arbitration Timing (E-DMAC Read → → → → DMAC 16-Byte Transmission → → → → CPU Read) Rev. 2.00 Mar 09, 2006 page 347 of 906 REJ09B0292-0200...
Page 374 Section 7 Bus State Controller (BSC) Figure 7.57 (b) Bus Arbitration Timing (E-DMAC Write → → → → DMAC 16-Byte Transmission → → → → CPU Read) Rev. 2.00 Mar 09, 2006 page 348 of 906 REJ09B0292-0200...
Page 375: Master Mode
The SH7616 is provided with the REFOUT pin to send a signal requesting the bus while refresh execution is being kept waiting. REFOUT is asserted while refresh execution is being kept waiting until the bus is acquired.
Page 376: Additional Items
Section 7 Bus State Controller (BSC) CKIO BRLS Address data Other bus control signals Figure 7.58 Bus Arbitration 7.10 Additional Items 7.10.1 Resets The bus state controller is completely initialized only in a power-on reset. All signals are immediately negated, regardless of whether or not the chip is in the middle of a bus cycle. Signal negation is simultaneous with turning the output buffer off.
Page 377: Access As Viewed From Cpu, Dmac Or E-Dmac
Section 7 Bus State Controller (BSC) 7.10.2 Access as Viewed from CPU, DMAC or E-DMAC The chip is internally divided into three buses: cache, internal, and peripheral. The CPU and cache memory are connected to the cache bus, the DMAC, E-DMAC and bus state controller are connected to the internal bus, and the low-speed peripheral devices and mode registers are connected to the peripheral bus.
Page 378: Stats1 And Stats0 Pins
7.10.3 STATS1 and STATS0 Pins The SH7616 has two pins, STATS1 and STATS0, to identify the bus master status. The signals output from these pins show the external access status. Encoded output is provided for the following categories: CPU (cache hit/cache disable), DMAC (external access only), E-DMAC, and Others (refresh, internal access, etc..).
Page 379: Bushiz Specification
BUSHiZ Specification 7.10.4 The BUSHiZ pin is needed when the SH7616 is connected to a PCI controller via a PCI bridge, and the PCI master and SH7616 share local memory on the SH7616 bus. By using this pin in combination with the WAIT pin, it is possible to place the bus and specific control signals in the high-impedance state while keeping the SH7616's internal state halted.
Page 380: Usage Notes
Section 7 Bus State Controller (BSC) 7.11 Usage Notes 7.11.1 Normal Space Access after Synchronous DRAM Write when Using DMAC Negation of the DQMn/WEn signal in a synchronous DRAM write and CSn assertion in an immediately following normal space access both occur at the same rising edge of CKIO (figure 7.61).
Page 381 Section 7 Bus State Controller (BSC) Normal space Synchronous DRAM write access access CKIO CS2 or CS3 RD/WR DQM/WEn (a) Burst write mode Synchronous DRAM Normal space write access access CKIO CS2 or CS3 RD/WR DQM/WEn (b) Single write mode Figure 7.61 Normal Space Access Immediately after Synchronous DRAM Write Rev.
Page 382: When Using Iφ: Eφ Clock Ratio Of 1: 1, 8-Bit Bus Width, And External Wait Input
Section 7 Bus State Controller (BSC) When Using Iφ φ φ φ : Eφ φ φ φ Clock Ratio of 1: 1, 8-Bit Bus Width, and External Wait Input 7.11.2 When using an Iφ: Eφ clock ratio of 1: 1 and an 8-bit bus width, at least 1.5 address hold cycles should be set.
Page 383: Section 8 Cache
Section 8 Cache Section 8 Cache Introduction This chip incorporates 4 kbytes of four-way, mixed instruction/data type cache memory. This memory can also be used as 2-kbyte RAM and 2 kbyte mixed instruction/data type cache memory by making a setting in the cache control register (CCR) (two-way cache mode). CCR can specify that either instructions or data do not use cache.
Page 384: Register Configuration
Section 8 Cache Address Number of bits Access space Tag address Entry address Byte address specification address in line Figure 8.2 Address Configuration 8.1.1 Register Configuration Table 8.1 shows the cache register configuration. Table 8.1 Register Configuration Name Abbrev. Initial Value Address Cache control register H'00...
Page 385 Section 8 Cache Bit 5—Write-Back Bit (WB): Specifies the cache operation method when the cache area is accessed. Bit 5: WB Description Write-through (Initial value) Write-back Bit 4—Cache Purge Bit (CP): When 1 is written to the CP bit, all cache entries and the valid bits, and LRU information of all ways are initialized to 0.
Page 386: Address Space And The Cache
Section 8 Cache Bit 1—Instruction Replacement Disable Bit (ID): ID is the bit for disabling instruction replacement. When this bit is 1, an instruction fetched from external memory is not written to the cache even if there is a cache miss. Cache data is, however, read or updated during cache hits. ID is valid only when CE is 1.
Page 387: Cache Operation
Section 8 Cache Cache Operation 8.4.1 Cache Reads This section describes cache operation when the cache is enabled and data is read from the CPU. One of the 64 entries is selected by the entry address part of the address output from the CPU on the cache address bus.
Page 388 Section 8 Cache When a cache miss occurs, the way for replacement is determined using the LRU information, and the read address from the CPU is written in the address array for that way. Simultaneously, the valid bit is set to 1. Since the 16 bytes of data for replacing the data array are simultaneously read, the address on the cache address bus is output to the internal address bus and 4 longwords are read consecutively.
Page 389: Write Access
Section 8 Cache 8.4.2 Write Access Write-Through Mode: Writing to external memory is performed regardless of whether or not there is a cache hit. The write address output to the cache address bus is used for comparison to the tag address of the cache’s address array. If they match, the write data output to the cache data bus in the following cycle is written to the cache data array.
Page 390 Section 8 Cache Write-Back Mode: When a cache hit occurs, the data is written to the data array of the matching way according to the entry address, byte address in the line, and access data size, and the update bit of that entry is set to 1. A write is performed only to the data array, not to external memory. A write hit is completed in 2 cycles (figure 8.6).
Page 391 Section 8 Cache Iφ pipeline stage Cache Address A Address B address Cache tag comparison Cache tag comparison Cache Address A data bus Data array write Internal Address A Address A Address A address Address A Address A Address A Address A Internal Address A...
Page 392: Cache-Through Access
Section 8 Cache 8.4.3 Cache-Through Access When reading or writing a cache-through area, the cache is not accessed. Instead, the cache address value is output to the internal address bus. For read operations, the read data output to the internal data bus is fetched and output to the cache data bus, as shown in figure 8.9. The read of the cache-through area is only performed on the address in question.
Page 393 Section 8 Cache reason, this cache uses a pseudo-LRU replacement algorithm that keeps track of the order of way access and replaces the oldest way. Six bits of data are used as the LRU information. The bits indicate the access order for 2 ways, as shown in figure 8.10.
Page 394: Cache Initialization
Section 8 Cache Table 8.3 LRU Information after Update Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Way 0 — — — Way 1 — — — Way 2 — — — Way 3 — — —...
Page 395: Cache Flushing
Section 8 Cache When writing to or reading the address obtained by adding H'40000000 to the address to be purged, the valid bit of the entry storing the address prior to addition are initialized to 0. 16 bytes are purged in each write, so a purge of 256 bytes of consecutive areas can be accomplished in 16 writes.
Page 396: Address Array Access
Section 8 Cache mapped on H'C0000000 to H'C00003FF, way 1 on H'C0000400 to H'C00007FF, way 2 on H'C0000800 to H'C0000BFF and way 3 on H'C0000C00 to H'C0000FFF. When the two-way mode is being used, the area H'C0000000 to H'C00007FF is accessed as 2 kbytes of on-chip RAM.
Page 397: Cache Use
Section 8 Cache Address array read: Entry Address — — address Number of bits Data — Tag address — V — information Number of bits 1 1 2 Address array write: Entry Address Tag address — V — address Number of bits 1 1 2 Data —...
Page 398: Purge Of Specific Lines
Section 8 Cache 8.5.2 Purge of Specific Lines There is no snoop function (for monitoring data rewrites), so specific lines of cache must be purged when the contents of cache memory and external memory differ as a result of an operation. For instance, when a DMA transfer is performed to the cache area, cache lines corresponding to the rewritten address area must be purged.
Page 399: Two-Way Cache Mode
Section 8 Cache To purge the cache using program logic, the data updates are detected by the program flow and the cache is then purged. For example, if the program inputs data from a disk, whenever reading of a unit (such as a sector) is completed, the buffer address used for reading or the entire cache is purged, thereby maintaining coherency.
Page 400: Usage Notes
Section 8 Cache H'00000000 H'C0000000 Way 0 H'C00003FF H'C0000400 Way 1 H'C00007FF H'FFFFFFFF Figure 8.16 Address Mapping of 2-kbyte RAM in the Two-Way Mode Usage Notes 8.6.1 Standby Disable the cache before entering the standby mode for power-down operation. After returning from standby, initialize the cache before use.
Page 401: Section 9 Ethernet Controller (Etherc)
Ethernet controller (EtherC) to perform transmission and reception of Ethernet/IEEE802.3 frames. The Ethernet controller is connected to dedicated transmit and receive Ethernet DMACs (E-DMACs) in the SH7616, and carries out high-speed data transfer to and from memory.
Page 402: Configuration
Section 9 Ethernet Controller (EtherC) 9.1.2 Configuration Figure 9.1 shows the configuration of the Ethernet controller. Transmit controller Receive controller Command status interface Figure 9.1 Configuration of Ethernet Controller (EtherC) Transmit Controller: Transmit data is stored in the transmit FIFO from memory via the transmit E-DMAC.
Page 403 Section 9 Ethernet Controller (EtherC) Receive Controller: After a frame is received via the MII, the receive controller carries out address information, frame length, CRC, and other checks, and the receive data is transferred to memory by the receive E-DMAC. The main functions of the receive controller are as follows: •...
Page 404: Pin Configuration
Section 9 Ethernet Controller (EtherC) 9.1.3 Pin Configuration The EtherC has signal pins compatible with the 18-pin MII specified in the IEEE802.3u standard, and three related signal pins to simplify connection to the PHY-LSI. The pin configuration are shown in table 9.1. Table 9.1 MII Pin Functions Abbre-...
Page 405: Ethernet Controller Register Configuration
Section 9 Ethernet Controller (EtherC) 9.1.4 Ethernet Controller Register Configuration The Ethernet controller (EtherC) has the nineteen 32-bit registers shown in table 9.2. Table 9.2 EtherC Registers Abbre- Name viation Initial Value Address EtherC mode register ECMR H'00000000 H'FFFFFD60 R/W * EtherC status register ECSR H'00000000...
Page 406: Register Descriptions
Section 9 Ethernet Controller (EtherC) Register Descriptions 9.2.1 EtherC Mode Register (ECMR) Bit: . . . — — — . . . — — — — Initial value: . . . R/W: . . . Bit: — — — PRCEF —...
Page 407 Section 9 Ethernet Controller (EtherC) Bit 12—Permit Receive CRC Error Frame (PRCEF): Specifies the treatment of a receive frame containing a CRC error. Bit 12: PRCEF Description Reception of a frame with a CRC error is treated as an error (Initial value) Reception of a frame with a CRC error is not treated as an error Note: When this bit is set to 1, the CRC error frame counter register (CEFCR: see section 9.2.14)
Page 408 Bit 2—External Loop Back Mode (ELB): The value in this register is output directly to the SH7616’s general-purpose external output pin (EXOUT). This is used for loopback mode directives, etc., in the PHY-LSI, using the EXOUT pin. Bit 2: ELB...
Page 409: Etherc Status Register (Ecsr)
Section 9 Ethernet Controller (EtherC) 9.2.2 EtherC Status Register (ECSR) Bit: . . . — — — . . . — — — — Initial value: . . . R/W: . . . Bit: — — — — — LCHNG Initial value: R/W * R/W *...
Page 410: Etherc Interrupt Permission Register (Ecsipr)
Section 9 Ethernet Controller (EtherC) Bit 0—Illegal Carrier Detection (ICD): Indicates that PHY-LSI has detected an illegal carrier on the line. This bit is cleared by writing 1 to it. Writing 0 to this bit has no effect. Bit 0: ICD Description PHY-LSI has not detected an illegal carrier on the line (Initial value)
Page 411: Phy Interface Register (Pir)
Section 9 Ethernet Controller (EtherC) Bit 1—Magic Packet Detection Interrupt Permission (MPDIP): Controls interrupt notification by the Magic Packet Detection bit. Bit 1: MPDIP Description Interrupt notification by MPD bit in ECSR is disabled (Initial value) Interrupt notification by MPD bit in ECSR is enabled Bit 0—Illegal Carrier Detection Interrupt Permission (ICDIP): Controls interrupt notification by the Illegal Carrier Detection bit.
Page 412: Mac Address High Register (Mahr)
Bits 31 to 0—MAC Address Bits 47 to 16 (MA47 to MA16): Used to set the upper 32 bits of the MAC address. Note: If the MAC address to be set in the SH7616 is 01-23-45-67-89-AB (hexadecimal), the value set in this register is H'01234567.
Page 413: Mac Address Low Register (Malr)
Bits 15 to 0—MAC Address Bits 15 to 0 (MA15 to MA0): Used to set the lower 16 bits of the MAC address. Note: If the MAC address to be set in the SH7616 is 01-23-45-67-89-AB (hexadecimal), the value set in this register is H'000089AB.
Page 414: Receive Frame Length Register (Rflr)
Initial value: R/W: This register specifies the maximum frame length (in bytes) that can be received by the SH7616 Bits 31 to 12—Reserved: These bits are always read as 0. The write value should always be 0. Bits 11 to 0—Receive Frame Length (RFL) H'000–H'5EE...
Page 415: Phy Interface Status Register (Psr)
Section 9 Ethernet Controller (EtherC) 9.2.8 PHY Interface Status Register (PSR) Bit: . . . — — — . . . — — — — Initial value: . . . R/W: . . . Bit: — — — — — —...
Page 416: Transmit Retry Over Counter Register (Trocr)
Section 9 Ethernet Controller (EtherC) 9.2.9 Transmit Retry Over Counter Register (TROCR) Bit: . . . — — — . . . — — — — Initial value: . . . R/W: . . . Bit: TROC15 TROC14 TROC13 TROC12 TROC11 TROC10 TROC9 TROC8 Initial value: R/W:...
Page 417: Single Collision Detect Counter Register (Scdcr)
Section 9 Ethernet Controller (EtherC) 9.2.10 Single Collision Detect Counter Register (SCDCR) This register is a 32-bit counter that indicates the number of collisions on all lines from a start of transmission. When the value in this register reaches H'FFFFFFFF, count-up is halted. The counter’s value is cleared to 0 by writing to this register.
Page 418: Delay Collision Detect Counter Register (Cdcr)
Section 9 Ethernet Controller (EtherC) 9.2.11 Delay Collision Detect Counter Register (CDCR) Bit: . . . — — — . . . — — — — Initial value: . . . R/W: . . . Bit: COLDC1 COLDC1 COLDC1 COLDC1 COLDC1 COLDC1 COLDC9 COLDC8...
Page 419: Lost Carrier Counter Register (Lccr)
Section 9 Ethernet Controller (EtherC) 9.2.12 Lost Carrier Counter Register (LCCR) Bit: . . . — — — . . . — — — — Initial value: . . . R/W: . . . Bit: LCC15 LCC14 LCC13 LCC12 LCC11 LCC10 LCC9 LCC8...
Page 420: Carrier Not Detect Counter Register (Cndcr)
Section 9 Ethernet Controller (EtherC) 9.2.13 Carrier Not Detect Counter Register (CNDCR) Bit: . . . — — — . . . — — — — Initial value: . . . R/W: . . . Bit: CNDC15 CNDC14 CNDC13 CNDC12 CNDC11 CNDC10 CNDC9 CNDC8 Initial value: R/W: Bit:...
Page 421: Illegal Frame Length Counter Register (Iflcr)
Section 9 Ethernet Controller (EtherC) 9.2.14 Illegal Frame Length Counter Register (IFLCR) Bit: . . . — — — . . . — — — — Initial value: . . . R/W: . . . Bit: IFLC15 IFLC14 IFLC13 IFLC12 IFLC11 IFLC10 IFLC9...
Page 422: Crc Error Frame Counter Register (Cefcr)
Section 9 Ethernet Controller (EtherC) 9.2.15 CRC Error Frame Counter Register (CEFCR) Bit: . . . — — — . . . — — — — Initial value: . . . R/W: . . . Bit: CEFC15 CEFC14 CEFC13 CEFC12 CEFC11 CEFC10 CEFC9 CEFC8 Initial value: R/W:...
Page 423: Frame Receive Error Counter Register (Frecr )
Section 9 Ethernet Controller (EtherC) 9.2.16 Frame Receive Error Counter Register (FRECR ) Bit: . . . — — — . . . — — — — Initial value: . . . R/W: . . . Bit: FREC15 FREC14 FREC13 FREC12 FREC11 FREC10 FREC9 FREC8 Initial value: R/W:...
Page 424: Too-Short Frame Receive Counter Register (Tsfrcr)
Section 9 Ethernet Controller (EtherC) 9.2.17 Too-Short Frame Receive Counter Register (TSFRCR) Bit: . . . — — — . . . — — — — Initial value: . . . R/W: . . . Bit: TSFC15 TSFC14 TSFC13 TSFC12 TSFC11 TSFC10 TSFC9 TSFC8 Initial value: R/W:...
Page 425: Too-Long Frame Receive Counter Register (Tlfrcr)
Section 9 Ethernet Controller (EtherC) 9.2.18 Too-Long Frame Receive Counter Register (TLFRCR) Bit: . . . — — — . . . — — — — Initial value: . . . R/W: . . . Bit: TLFC15 TLFC14 TLFC13 TLFC12 TLFC11 TLFC10 TLFC9 TLFC8 Initial value:...
Page 426: Residual-Bit Frame Counter Register (Rfcr)
Section 9 Ethernet Controller (EtherC) 9.2.19 Residual-Bit Frame Counter Register (RFCR) Bit: . . . — — — . . . — — — — Initial value: . . . R/W: . . . Bit: RFC15 RFC14 RFC13 RFC12 RFC11 RFC10 RFC9 RFC8...
Page 427: Multicast Address Frame Counter Register (Mafcr)
Section 9 Ethernet Controller (EtherC) 9.2.20 Multicast Address Frame Counter Register (MAFCR) Bit: . . . — — — . . . — — — — Initial value: . . . R/W: . . . Bit: MAFC15 MAFC14 MAFC13 MAFC12 MAFC11 MAFC10 MAFC9 MAFC8 Initial value: R/W:...
Page 428: Operation
Section 9 Ethernet Controller (EtherC) Operation When a transmit command is issued from the transmit E-DMAC, the EtherC starts transmission in accordance with a predetermined transmission procedure. When the specified number of words have been transferred, transmission of one frame is terminated. When an own-address frame (including a broadcast frame) is received, the EtherC transfers the frame to the receive E-DMAC while carrying out format checks.
Page 429 Section 9 Ethernet Controller (EtherC) TE set FDPX Start of transmission Idle (preamble transmission) Carrier Carrier HDPX detection Transmission non-detection halted Retrans- TE reset HDPX mission initiation Carrier FDPX detection Collision Reset Carrier detection Carrier Carrier Retransmission non-detection detection processing Collision Failure of 15 retransmission...
Page 430: Reception
Section 9 Ethernet Controller (EtherC) Note: If a collision or the carrier-not-detected state occurs during data transmission, these are reported as interrupt sources. 4. After waiting for the frame interval time, the transmitter enters the idle state, and if there is more transmit data, continues transmitting.
Page 431 Section 9 Ethernet Controller (EtherC) Illegal carrier detection Rx-DV negation Start of frame Wait for SFD Idle reception reception Preamble RE set detection reception Reception halted RE reset Promiscuous and other station Destination destination address address reception Own destination Reset address or broadcast or multicast...
Page 432: Mii Frame Timing
Section 9 Ethernet Controller (EtherC) 9.3.3 MII Frame Timing Figures 9.4 (a) to (f) show the timing for various kinds of MII frames. The normal timing for frame transmission is shown in figure 9.4 (a), the timing in the case of a collision during transmission in figure 9.4 (b), and the timing in the case of an error during transmission in figure 9.4 (c).
Page 433 Section 9 Ethernet Controller (EtherC) TX-CLK TX-EN TXD3 – Preamble Data TXD0 TX-ER Figure 9.4 (c) MII Frame Transmit Timing (Transmit Error) RX-CLK RX-DV RXD3 – Preamble Data RXD0 RX-ER Figure 9.4 (d) MII Frame Receive Timing (Normal Reception) RX-CLK RX-DV RXD3 –...
Page 434: Accessing Mii Registers
Section 9 Ethernet Controller (EtherC) 9.3.4 Accessing MII Registers MII registers in the PHY-LSI are accessed via the SH7616’s PHY interface register (PIR). Connection is made as a serial interface in accordance with the MII frame format specified in IEEE802.3u.
Page 435 Section 9 Ethernet Controller (EtherC) 1. The MII register write procedure is shown in figure 9.6 (a). 2. The bus release procedure is shown in figure 9.6 (b). 3. The MII register read procedure is shown in figure 9.6 (c). 4.
Page 436 Section 9 Ethernet Controller (EtherC) (1) Write to PHY interface register MMD = 0 MDC = 1 (2) Read from PHY interface register read MMD = 0 MMC = 1 MDI is read data 1-bit data read timing relationship (3) Write to PHY interface register MMD = 0 MDC = 0...
Page 437: Magic Packet Detection
Magic Packets can be found in the technical documentation published by AMD Corporation. The procedure for using the WOL function with the SH7616 is as follows. 1. Disable interrupt source output by means of the various interrupt enable/mask registers.
Page 438: Cpu Operating Mode And Ethernet Controller Operation
When the SH7616 has been placed in standby mode, the CPU, DSP, and bus state controller are among the functions halted. When DRAM is connected, refreshing is also halted, and therefore initialization of memory, etc., is necessary after recovery, in the same...
Page 439: Cam Match Signal Input Function
9.7). The EtherC receives the result of comparison of a destination address corresponding to signals (RXD3 to RXD0) fetched from the MII as a signal from a CAMSEN pin and selects whether the current frame is received or discarded. SH7616 MII (RX-DV, RXD3 to RXD0) PHY-LSI...
Page 440 EtherC/E-DMAC status register (EESR) and this can be reflected as the write-back information of the descriptor. Table 9.3 Processing of Receive Frames CAMSEN Input Frame Type Normal Mode Promise-CAS Mode Asserted SH7616 MAC address Discarded Discarded (address is Broadcast address Discarded Discarded matched)
Page 441: Connection To Phy-Lsi
Section 9 Ethernet Controller (EtherC) Connection to PHY-LSI Figure 9.9 shows example of connection to an PHY-LSI AM79C873 (Advanced Micro Devices, Inc). Figure 9.10 shows example of connection to a DP83843 (National Semiconductor Corporation). MII (Media independent interface) SH7616 AM79C873 TX-ER TXER ETXD3 ETXD3...
Page 442 Section 9 Ethernet Controller (EtherC) MII (Media independent interface) SH7616 DP83843 TX-ER TX_ER ETXD3 TXD3 ETXD2 TXD2 ETXD1 TXD1 ETXD0 TXD0 TX-EN TX_EN TX-CLK TX_CLK MDIO MDIO ERXD3 RXD3 ERXD2 RXD2 ERXD1 RXD1 ERXD0 RXD0 RX-CLK RX_CLK RX-DV RX_DV RX-ER RX_ER Figure 9.10 Example of Connection to DP83843...
Page 443: Section 10 Ethernet Controller Direct Memory Access Controller (E-Dmac)
10.1 Overview The SH7616 has an on-chip two-channel direct memory access controller (E-DMAC) directly connected to the Ethernet controller (EtherC). A large proportion of buffer management is controlled by the E-DMAC itself using descriptors. This lightens the load on the CPU and enables efficient data transfer control to be achieved.
Page 444: Configuration
Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) 10.1.2 Configuration Figure 10.1 shows the configuration of the E-DMAC, and the descriptors and transmit/receive buffers in memory. E-DMAC SH7616 Tx FIFO Descriptor information Transmit DMAC Internal EtherC interface Rx FIFO...
Page 445: Descriptor Management System
Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) 10.1.3 Descriptor Management System The E-DMAC manages the transmit/receive buffers by means of corresponding transmit/receive descriptor lists. Transmission: The transmit E-DMAC fetches a transmit buffer address from the top of the transmit descriptor list, and transfers the transmit data in the buffer to the transmit FIFO.
Page 446 Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) Table 10.1 E-DMAC Registers Abbre- Name viation Initial Value Address E-DMAC mode register EDMR H'00000000 H'FFFFFD00 E-DMAC transmit request register EDTRR H'00000000 H'FFFFFD04 E-DMAC receive request register EDRRR H'00000000 H'FFFFFD08 Transmit descriptor list address register TDLAR H'00000000 H'FFFFFD0C...
Page 447: Register Descriptions
Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) 10.2 Register Descriptions 10.2.1 E-DMAC Mode Register (EDMR) The E-DMAC mode register specifies the operating mode of the E-DMAC. The settings in this register are normally made in the initialization process following a reset. Note: Operating mode settings must not be changed while the transmitter and receiver are enabled.
Page 448: E-Dmac Transmit Request Register (Edtrr)
Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 0—Software Reset (SWR): The EtherC and E-DMAC can be initialized by software. These bits should only be written with 0. Bit 0: SWR Description EtherC and E-DMAC reset is cleared (Initial value) EtherC and E-DMAC are reset Notes: 1.
Page 449: E-Dmac Receive Request Register (Edrrr)
Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) 10.2.3 E-DMAC Receive Request Register (EDRRR) The E-DMAC receive request register issues receive directives to the E-DMAC. Bit: . . . — — — . . . — — — — Initial value: .
Page 450: Transmit Descriptor List Address Register (Tdlar)
Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) 10.2.4 Transmit Descriptor List Address Register (TDLAR) TDLAR specifies the start address of the transmit descriptor list. Descriptors have a boundary configuration in accordance with the descriptor length indicated by the DL bit in EDMR. Bit: TDLA31 TDLA30 TDLA29 TDLA28 TDLA27 TDLA26 TDLA25 TDLA24 Initial value:...
Page 451: Receive Descriptor List Address Register (Rdlar)
Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) 10.2.5 Receive Descriptor List Address Register (RDLAR) RDLAR specifies the start address of the receive descriptor list. Descriptors have a boundary configuration in accordance with the descriptor length indicated by the DL bit in EDMR. Bit: RDLA31 RDLA30 RDLA29 RDLA28 RDLA27 RDLA26 RDLA25 RDLA24 Initial value:...
Page 452: Etherc/E-Dmac Status Register (Eesr)
Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) 10.2.6 EtherC/E-DMAC Status Register (EESR) EESR shows communication status information for both the E-DMAC and the EtherC. The information in this register is reported in the form of interrupt sources. Individual bits are cleared by writing 1 to them.
Page 453 Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) transferred to memory when DMA transfer becomes possible. When the frame counter value falls below 8, another frame is received. Bit 23—Reserved: These bits are always read as 0. The write value should always be 0. Bit 22—EtherC States Register Interrupt (ECI): Indicates that an interrupt due to an EtherC status register (ECSR) source has been detected.
Page 454 Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 19—Transmit FIFO Underflow (TFUF): Indicates that underflow has occurred in the transmit FIFO during frame transmission. Incomplete data is sent onto the line. Bit 19: TFUF Description Underflow has not occurred (Initial value) Underflow has occurred (interrupt source) Note: Whether E-DMAC operation continues or halts after underflow is controlled by the E-DMAC...
Page 455 Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bits 15 to 13—Reserved: These bits are always read as 0. The write value should always be 0. Bit 12—Illegal Transmit Frame (ITF): Indicates that the transmit frame length specification is less than four bytes.
Page 456 Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 7—Receive Multicast Address Frame (RMAF): Indicates that a multicast address frame has been received. Bit 7: RMAF Description Multicast address frame has not been received (Initial value) Multicast address frame has been received (interrupt source) Bits 6—Reserved: This bit should only be written with 0.
Page 457 Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 1—PHY-LSI Receive Error (PRE): Indicates an error notification from the MII (PHY-LSI) Bit 1: PRE Description PHY-LSI receive error not detected (Initial value) PHY-LSI receive error detected (interrupt source) Bit 0—CRC Error on Received Frame (CERF): Indicates that a CRC error has been detected in the received frame.
Page 458: Etherc/E-Dmac Status Interrupt Permission Register (Eesipr)
Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) 10.2.7 EtherC/E-DMAC Status Interrupt Permission Register (EESIPR) EESIPR enables interrupts corresponding to individual bits in the EtherC/E-DMAC status register. An interrupt is enabled by writing 1 to the corresponding bit. In the initial state, interrupts are not enabled.
Page 459 Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 23—Reserved: This bit is always read as 0. The write value should always be 0. Bit 22—EtherC Status Register Interrupt Permission (ECIP): Enables interrupts due to EtherC status register sources. Bit 22: ECIP Description EtherC status interrupts are disabled...
Page 460 Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 17—Receive Descriptor Exhausted Interrupt Permission (RDEIP): Enables the receive descriptor exhausted interrupt. Bit 17: RDEIP Description Receive descriptor exhausted interrupt is disabled (Initial value) Receive descriptor exhausted interrupt is enabled Bit 16—Receive FIFO Overflow Interrupt Permission (RFOFIP): Enables the receive FIFO overflow interrupt.
Page 461 Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 9—Collision Detect Interrupt Permission (CDIP): Enables the collision detect interrupt. Bit 9: CDIP Description Collision detect interrupt is disabled (Initial value) Collision detect interrupt is enabled Bit 8—Transmit Retry Over Interrupt Permission (TROIP): Enables the transmit retry over interrupt.
Page 462 Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 3—Receive Too-Long Frame Interrupt Permission (RTLFIP): Enables the receive too-long frame interrupt. Bit 3: RTLFIP Description Receive too-long frame interrupt is disabled (Initial value) Receive too-long frame interrupt is enabled Bit 2—Receive Too-Short Frame Interrupt Permission (RTSFIP): Enables the receive too-short frame interrupt.
Page 463: Transmit/Receive Status Copy Enable Register (Trscer)
Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) 10.2.8 Transmit/Receive Status Copy Enable Register (TRSCER) TRSCER specifies whether or not transmit and receive status information reported by bits in the EtherC/E-DMAC status register is to be indicated in the corresponding descriptor. The bits in this register correspond to EtherC/E-DMAC status register EESR[15 to 0].
Page 464: Receive Missed-Frame Counter Register (Rmfcr)
Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) 10.2.9 Receive Missed-Frame Counter Register (RMFCR) RMFCR is a 16-bit counter that indicates the number of frames missed (discarded, and not transferred to the receive buffer) during reception. When the receive FIFO overflows, the receive frames in the FIFO are discarded.
Page 465: Transmit Fifo Threshold Register (Tftr)
Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) 10.2.10 Transmit FIFO Threshold Register (TFTR) TFTR specifies the transmit FIFO threshold at which the first transmission is started. The actual threshold is 4 times the set value. The EtherC starts transmission when the amount of data in the transmit FIFO exceeds the number of bytes specified by this register, when the transmit FIFO is full, or when 1-frame write is executed.
Page 466 Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bits 10 to 0—Transmit FIFO Threshold 10 to 0 (TFT10 to TFT0) Bits 10 to 0: Description H'00 Store-and-forward mode (transmission starts when one frame of data is written or transmit FIFO is full) (Initial value) H'01 4 bytes...
Page 467: Fifo Depth Register (Fdr)
Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) 10.2.11 FIFO Depth Register (FDR) FDR specifies the depth (size) of the transmit and receive FIFOs. Bit: . . . — — — . . . — — — — Initial value: .
Page 468: Receiver Control Register (Rcr)
Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 2 to 0—Receive FIFO Depth (RFD): Specifies 256 bytes to 2 kbytes in 256-byte units as the depth (size) of the receive FIFO. The actual FIFO depth is 256 times the set value. The setting cannot be changed after transmission/reception has started.
Page 469: E-Dmac Operation Control Register (Edocr)
Illegal memory address detected. Can be cleared by writing 0 Note: This error occurs if the memory address setting in the descriptor used by the E-DMAC is illegal. Bit 1—E-DMAC Halted (EDH): When the SH7616’s NMI input pin is asserted, E-DMAC operation is halted. Bit 1: EDH...
Page 470: Receiving-Buffer Write Address Register (Rbwar)
Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bits 0—Reserved: This bit is always read as 0. The write value should always be 0. 10.2.14 Receiving-Buffer Write Address Register (RBWAR) This is the register for storing the buffer address to be written in the receiving buffer when the E- DMAC writes data in the receiving buffer.
Page 471: Receiving-Descriptor Fetch Address Register (Rdfar)
Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) 10.2.15 Receiving-Descriptor Fetch Address Register (RDFAR) This is the register for storing the descriptor start address that is required when the E-DMAC fetches descriptor information from the receiving descriptor . Which receiving descriptor information is used for processing by the E-DMAC can be recognized by monitoring addresses displayed in this register.
Page 472: Transmission-Buffer Read Address Register (Tbrar)
Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) 10.2.16 Transmission-Buffer Read Address Register (TBRAR) This is the register for storing the buffer address to be read in the transmission buffer when the E- DMAC reads data from the transmission buffer. Which addresses in the transmission buffer are processed by the E-DMAC can be recognized by monitoring addresses displayed in this register.
Page 473: Transmission-Descriptor Fetch Address Register (Tdfar)
Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) 10.2.17 Transmission-Descriptor Fetch Address Register (TDFAR) This is the register for storing the descriptor start address that is required when the E-DMAC fetches descriptor information from the transmission descriptor . Which transmission descriptor information is used for processing by the E-DMAC can be recognized by monitoring addresses displayed in this register.
Page 474: Operation
Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) 10.3 Operation The E-DMAC is connected to the EtherC, and performs efficient transfer of transmit/receive data between the EtherC and memory (buffers) without the intervention of the CPU. The E-DMAC itself reads control information, including buffer pointers called descriptors, relating to the buffers. The E-DMAC reads transmit data from the transmit buffer and writes receive data to the receive buffer in accordance with this control information.
Page 475 Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) Transmit Descriptor 0 (TD0): TD0 indicates the transmit frame status. The CPU and E-DMAC use TD0 to report the frame transmission status. Bit 31—Transmit Descriptor Active (TACT): Indicates that this descriptor is active. The CPU sets this bit after transmit data has been transferred to the transmit buffer.
Page 476 Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 29: Bit 28: TFP1 TFP0 Description Frame transmission for transmit buffer indicated by this descriptor continues (frame is not concluded) Transmit buffer indicated by this descriptor contains end of frame (frame is concluded) Transmit buffer indicated by this descriptor is start of frame (frame is not concluded)
Page 477 Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) Transmit Descriptor 1 (TD1): Specifies the transmit buffer length (maximum 64 kbytes). Bits 31 to 16—Transmit Buffer Data Length (TDL): These bits specify the valid transfer byte length in the corresponding transmit buffer. Note: When the one frame/multi-buffer system is specified (TD0 and TFP = 10 or 00), the transfer byte length specified in the descriptors at the start and midway can be set in byte units.
Page 478 Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) Receive descriptor Receive buffer 31 30 29 28 RFS 26 to RFS0 Valid receive data 16 15 Padding (4 bytes) Figure 10.3 Relationship between Receive Descriptor and Receive Buffer Receive Descriptor 0 (RD0): RD0 indicates the receive frame status. The CPU and E-DMAC use RD0 to report the frame transmission status.
Page 479 Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 30—Receive Descriptor List Last (RDLE): Indicates that this descriptor is the last in the receive descriptor list. After completion of the corresponding buffer transfer, the E-DMAC references the first receive descriptor. This specification is used to set a ring configuration for the receive descriptors.
Page 480 Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) Note: This bit is set to 1 when any of Receive Frame Status bit 9, bit 7, bits 4 to 0 is set. When this bit is set, the Receive Frame Error bit (bit 27: RFE) is set to 1. •...
Page 481: Transmission
Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) 10.3.2 Transmission When the transmitter is enabled and the transmit request bit (TR) is set in the E-DMAC transmit request register (EDTRR), the E-DMAC reads the descriptor used last time from the transmit descriptor list (in the initial state, the descriptor indicated by the transmission descriptor start address register (TDLAR)).
Page 482 Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) Transmission flowchart SH7616 + memory E-DMAC Transmit FIFO EtherC Ethernet EtherC/E-DMAC initialization Descriptor and transmit buffer setting Transmit directive Descriptor read Transmit data transfer Descriptor write-back Descriptor read Transmit data transfer...
Page 483: Reception
Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) 10.3.3 Reception When the receiver is enabled and the CPU sets the receive request bit (RR) in the E-DMAC receive request register (EDRRR), the E-DMAC reads the descriptor following the previously used one from the receive descriptor list (in the initial state, the descriptor indicated by the transmission descriptor start address register (TDLAR)), and then enters the receive-standby state.
Page 484 Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) Reception flowchart SH7616 + memory E-DMAC Receive FIFO EtherC Ethernet EtherC/E-DMAC initialization Descriptor and transmit buffer setting Start of reception Descriptor read Frame reception Receive data transfer Descriptor write-back Descriptor read...
Page 485: Multi-Buffer Frame Transmit/Receive Processing
Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) 10.3.4 Multi-Buffer Frame Transmit/Receive Processing Multi-Buffer Frame Transmit Processing: If an error occurs during multi-buffer frame transmission, the processing shown in figure 10.6 is carried out. Where the transmit descriptor is shown as inactive (TACT bit = 0) in the figure, buffer data has already been transmitted normally, and where the transmit descriptor is shown as active (TACT bit = 1), buffer data has not been transmitted.
Page 486 Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) 1), this indicates a buffer for which reception has not yet been performed. If a frame receive error occurs in the first descriptor part where the RACT bit = 1 in the figure, reception is halted immediately and a status write-back to the descriptor is performed.
Page 487: Section 11 Direct Memory Access Controller (Dmac)
Section 11 Direct Memory Access Controller (DMAC) Section 11 Direct Memory Access Controller (DMAC) 11.1 Overview A two-channel direct memory access controller (DMAC) is included on-chip. The DMAC can be used in place of the CPU to perform high-speed data transfers between external devices equipped with DACK (transfer request acknowledge signal), external memories, on-chip memory, and memory-mapped external devices.
Page 488 Section 11 Direct Memory Access Controller (DMAC)  Two on-chip peripheral modules (excluding DMAC, BSC, UBC, cache-memory, E- DMAC, and EtherC)  On-chip memory and memory-mapped external device  Two on-chip memories  On-chip memory and on-chip peripheral modules (excluding DMAC, BSC, UBC, cache- memory, E-DMAC, and EtherC) ...
Page 489: Block Diagram
Section 11 Direct Memory Access Controller (DMAC) 11.1.2 Block Diagram Figure 11.1 shows the DMAC block diagram. On-chip memory On-chip SARn peripheral module DARn TCRn Iteration control DREQn Register control On-chip peripheral CHCRn module request Start-up control DACKn DMAOR DEIn Request External priority...
Page 490: Pin Configuration
Section 11 Direct Memory Access Controller (DMAC) 11.1.3 Pin Configuration Table 11.1 shows the DMAC pin configuration. Table 11.1 Pin Configuration Channel Name Symbol Function DMA transfer request DREQ0 DMA transfer request input from external device to channel 0 DMA transfer request DACK0 DMA transfer request acknowledge output acknowledge...
Page 491: Register Configuration
Section 11 Direct Memory Access Controller (DMAC) 11.1.4 Register Configuration Table 11.2 summarizes the DMAC registers. The DMAC has a total of 13 registers. Each channel has six control registers. One control register is shared by both channels. Table 11.2 Register Configuration Initial Access Size *...
Page 492: Register Descriptions
Section 11 Direct Memory Access Controller (DMAC) 11.2 Register Descriptions 11.2.1 DMA Source Address Registers 0 and 1 (SAR0, SAR1) Bit: … … Initial value: — — — … — — — — R/W: … DMA source address registers 0 and 1 (SAR0 and SAR1) are 32-bit read/write registers that specify the source address of a DMA transfer.
Page 493: Dma Transfer Count Registers 0 And 1 (Tcr0, Tcr1)
Section 11 Direct Memory Access Controller (DMAC) 11.2.3 DMA Transfer Count Registers 0 and 1 (TCR0, TCR1) Bit: — — — — — — — — Initial value: R/W: Bit: … … Initial value: — — — … — — —...
Page 494 Section 11 Direct Memory Access Controller (DMAC) DMA channel control registers 0 and 1 (CHCR0 and CHCR1) are 32-bit read/write registers that control the DMA transfer mode. They also indicate the DMA transfer status. Only the lower 16 of the 32 bits are valid. They should be read and written as 32-bit values, including the upper 16 bits. The registers are initialized to H'00000000 by a reset and in standby mode.
Page 495 Section 11 Direct Memory Access Controller (DMAC) Bits 11 and 10—Transfer Size Bits (TS1, TS0): Select the DMA transfer size. When 11 is set to bits TS1 and TS0 (in the 16-byte unit), request mode is available only in auto-request mode and at edge detection in external request mode.
Page 496 Section 11 Direct Memory Access Controller (DMAC) Bit 7—Acknowledge Level Bit (AL): Selects whether the DACKn signal is an active-high signal or an active-low signal. The AL bit is initialized to 0 by a reset and in standby mode. Its value is retained during a module standby.
Page 497 Section 11 Direct Memory Access Controller (DMAC) Bit 3—Transfer Address Mode Bit (TA): Selects the DMA transfer address mode. The TA bit is initialized to 0 by a reset and in standby mode. Its value is retained during a module standby. Bit 3: TA Description Dual address mode...
Page 498: Dma Vector Number Registers 0 And 1 (Vcrdma0, Vcrdma1)
Section 11 Direct Memory Access Controller (DMAC) Bit 0—DMA Enable Bit (DE): Enables or disables DMA transfers. In auto-request mode, the transfer starts when this bit or the DME bit in DMAOR is set to 1. The NMIF and AE bits in DMAOR and the TE bit must be all set to 0.
Page 499: Dma Request/Response Selection Control Registers 0 And 1 (Drcr0, Drcr1)
Section 11 Direct Memory Access Controller (DMAC) 11.2.6 DMA Request/Response Selection Control Registers 0 and 1 (DRCR0, DRCR1) Bit: — — — Initial value: R/W: DMA request/response selection control registers 0 and 1 (DRCR0, DRCR1) are 8-bit read/write registers that set the DMAC transfer request source. They are written as 8-bit values. They are initialized to H'00 by a reset, but retain their values in standby mode and a module standby.
Page 500 Section 11 Direct Memory Access Controller (DMAC) Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: Description Reserved (setting prohibited) SCIF channel 2 RXI (on-chip SCI with FIFO channel 2 receive-data-full interrupt request) * SCIF channel 2 TXI (on-chip SCI with FIFO channel 2 transmit-data-empty interrupt request) * Reserved (setting prohibited) TPU TGI0A (TPU input capture channel 0A interrupt...
Page 501: Dma Operation Register (Dmaor)
Section 11 Direct Memory Access Controller (DMAC) 11.2.7 DMA Operation Register (DMAOR) Bit: … — — — … — — — — Initial value: … R/W: … Bit: — — — — NMIF Initial value: R/(W) * R/(W) * R/W: Note: * Only 0 can be written, to clear the flag.
Page 502 Section 11 Direct Memory Access Controller (DMAC) Bit 2—Address Error Flag Bit (AE): This flag indicates that an address error has occurred in the DMAC. When the AE bit is set to 1, DMA transfer cannot be enabled even if the DE bit in the DMA channel control register (CHCR) is set to 1.
Page 503: Operation
Section 11 Direct Memory Access Controller (DMAC) 11.3 Operation When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority; when the transfer-end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto-request, external request, and on-chip module request.
Page 504 Section 11 Direct Memory Access Controller (DMAC) Start Initial settings (SAR, DAR, TCR, CHCR, VCRDMA, DRCR, DMAOR) DME = 1 and NMIF, AE, TE = 0? Has a transfer request been generated?* mode, transfer request mode, DREQ detec- tion method? Transfer TCR-1 →...
Page 505: Dma Transfer Requests
Section 11 Direct Memory Access Controller (DMAC) 11.3.2 DMA Transfer Requests DMA transfer requests are usually generated in either the data transfer source or destination, but they can also be generated by devices that are neither the source nor the destination. Transfers can be requested in three modes: auto-request, external request, and on-chip peripheral module request.
Page 506 Section 11 Direct Memory Access Controller (DMAC) External Request Mode: In this mode a transfer is started by a transfer request signal (DREQn) from an external device. Choose one of the modes shown in table 11.4 according to the application system.
Page 507 Section 11 Direct Memory Access Controller (DMAC) Table 11.5 Selecting the External Request Signal with the DS and DL Bits CHCR External Request Low-level detection (can only be set in cycle-steal mode) High-level detection (can only be set in cycle-steal mode) Falling-edge detection Rising-edge detection On-Chip Module Request Mode: In this mode, transfers are started by a transfer request signal...
Page 508 Section 11 Direct Memory Access Controller (DMAC) Table 11.6 Selecting On-Chip Peripheral Module Request Mode with the AR and RS Bits DMA Transfer Transfer Transfer Request Request Transfer Destina- DREQ RS4 RS3 RS2 RS1 RS0 Source Signal Source tion Mode Setting SCIF channel 1 SCFRDR1 Any...
Page 509: Channel Priorities
Section 11 Direct Memory Access Controller (DMAC) For outputting transfer request from the SCIF, SIOF, SIO, and TPU, the corresponding interrupt enable bits must be set to output the interrupt signals. Note that transfer request signals from on- chip peripheral modules (interrupt request signals) are sent not just to the DMAC but to the CPU as well.
Page 510 Section 11 Direct Memory Access Controller (DMAC) DREQ0 DREQ1 Channel 0 Channel 1 Channel 0 source source source cycle Channel 0 Channel 1 destination destination Figure 11.4 Fixed Mode DMA Transfer in Cycle-Steal Mode (Dual Address, DREQn Low-Level Detection) Round-Robin Mode: Switches the priority of channel 0 and channel 1, shifting their ability to receive transfer requests.
Page 511 Section 11 Direct Memory Access Controller (DMAC) Transfer requests Waiting channel DMAC operation Channel priority order 1. Requests occur 2. Channel 1 1 > 0 in channels transfer starts 0 and 1 Priority changes 3. Channel 1 0 > 1 transfer ends 4.
Page 512: Dma Transfer Types
Section 11 Direct Memory Access Controller (DMAC) 11.3.4 DMA Transfer Types It can operate in single address mode or dual address mode, as defined by how many bus cycles the DMAC takes to access the transfer source and transfer destination. The actual transfer operation timing varies with the DMAC bus mode used: cycle-steal mode or burst mode.
Page 513 Section 11 Direct Memory Access Controller (DMAC) External address bus External data bus Chip External DMAC memory External device with DACK DACKn DREQn : Data flow Figure 11.6 Data Flow in Single Address Mode Two types of transfers are possible in single address mode: 1) transfers between external devices with DACK and memory-mapped external devices;...
Page 514 Section 11 Direct Memory Access Controller (DMAC) CKIO Address output to external A24–A0 memory space Write strobe signal to external memory space Data output from external D31–D0 device with DACK DACK signal (active low) to external DACKn device with DACK a.
Page 515 Section 11 Direct Memory Access Controller (DMAC) • Dual Address Mode In dual address mode, both the transfer source and destination are accessed (selectable) by address. The source and destination can be located externally or internally. The DMAC accesses the source in the read cycle and the destination in the write cycle, so the transfer is performed in two separate bus cycles.
Page 516 Section 11 Direct Memory Access Controller (DMAC)  Transfer between on-chip memory and external memory  Transfer between on-chip peripheral module (excluding DMAC, BSC, UBC, cache, E- DMAC, and EtherC) and on-chip peripheral module (excluding DMAC, BSC, UBC, cache, E-DMAC, and EtherC)* Note: * Access size permitted by peripheral module register used as transfer source or transfer destination (excluding DMAC, BSC, UBC, cache, E-DMAC, and EtherC).
Page 517 Section 11 Direct Memory Access Controller (DMAC) Bus Modes: There are two bus modes: cycle-steal and burst. Select the mode with the TB bits in CHCR0 and CHCR1. • Cycle-Steal Mode In cycle-steal mode, the bus right is given to another bus master each time the DMAC completes one transfer.
Page 518 Section 11 Direct Memory Access Controller (DMAC) • Burst Mode In burst mode, once the DMAC gets the bus, the transfer continues until the transfer end condition is satisfied. When external request mode is used with level detection of the DREQ pin, however, negating DREQ will pass the bus to the other bus master after completion of the bus cycle of the DMAC that currently has an acknowledged request, even if the transfer end conditions have not been satisfied.
Page 519 Section 11 Direct Memory Access Controller (DMAC) Relationship of Request Modes and Bus Modes by DMA Transfer Category: Table 11.8 shows the relationship between request modes, bus modes, etc., by DMA transfer category. Table 11.8 Relationship of Request Modes and Bus Modes by DMA Transfer Category Address Transfer Request Mode *...
Page 520 Section 11 Direct Memory Access Controller (DMAC) Address Transfer Request Mode * Mode * Mode Transfer Range Size (Byte) 1/2/4 * Dual Between internal memory and internal Automatic peripheral module 1/2/4 * Internal peripheral module * 1/2/4/16 * Between internal memory and external External memory* Automatic...
Page 521 Section 11 Direct Memory Access Controller (DMAC) Table 11.9 shows the combinations of request mode, bus mode, and address mode that can be specified in the external request mode. Table 11.9 Combinations of Request Mode, Bus Mode, and Address Mode Specifiable in the External Request Mode Dual Address Mode Single Address Mode...
Page 522: Number Of Bus Cycles
Section 11 Direct Memory Access Controller (DMAC) 11.3.5 Number of Bus Cycles The number of states in the bus cycle when the DMAC is the bus master is controlled by the bus state controller (BSC) just as it is when the CPU is the bus master. For details, see section 7, Bus State Controller (BSC).
Page 523 Section 11 Direct Memory Access Controller (DMAC) Clock DACKn (Active high) 0.5 cycles DMAC Invalid DMAC read write write Address DMAC read Basic timing 1 wait inserted Figure 11.14 DACKn Output in Ordinary Space Accesses (AM = 0) Clock DACKn (Active high) DMAC Invalid...
Page 524 Section 11 Direct Memory Access Controller (DMAC) Clock DACKn (Active high) Invalid write Address CPU H DMAC read H DMAC read L DMAC write Basic timing Notes: 1. H: MSB side 2. L: LSB side Figure 11.16 DACKn Output in Ordinary Space Accesses (AM = 0, Longword Access to 16-Bit External Device) Clock DACKn...
Page 525 Section 11 Direct Memory Access Controller (DMAC) Acknowledge Signal Output when External Memory Is Set as Synchronous DRAM: When external memory is set as synchronous DRAM, DACKn output becomes valid simultaneously with the start of the DMA address, and becomes invalid when the address output ends. When external memory is set as synchronous DRAM auto-precharge and AM = 0, the acknowledge signal is output across the row address, read command, wait and read address of the DMAC read (figure 11.19).
Page 526 Section 11 Direct Memory Access Controller (DMAC) Clock DACKn Read (Active high) command Column address address address Address Read Invalid read DMAC read DMAC write (basic timing) (basic timing) Figure 11.20 DACKn Output in Synchronous DRAM Single Read (Auto-Precharge, AM = 0) Clock DACKn (Active high)
Page 527 Section 11 Direct Memory Access Controller (DMAC) When external memory is set as bank active synchronous DRAM, during a burst read the acknowledge signal is output across the read command, wait and read address when the row address is the same as the previous address output (figure 11.22). When the row address is different from the previous address, the acknowledge signal is output across the precharge, row address, read command, wait and read address (figure 11.23).
Page 528 Section 11 Direct Memory Access Controller (DMAC) When external memory is set as bank active synchronous DRAM, during a single read the acknowledge signal is output across the read command, wait and read address when the row address is the same as the previous address output (figure 11.24). When the row address is different from the previous address, the acknowledge signal is output across the precharge, row address, read command, wait and read address (figure 11.25).
Page 529 Section 11 Direct Memory Access Controller (DMAC) When external memory is set as bank active synchronous DRAM, during a write the acknowledge signal is output across the wait and column address when the row address is the same as the previous address output (figure 11.26).
Page 530 Section 11 Direct Memory Access Controller (DMAC) • Synchronous DRAM one-cycle write When a one-cycle write is performed to synchronous DRAM, the DACKn signal is synchronized with the rising edge of the clock. A request by the request signal is accepted while the clock is high during DACKn output.
Page 531 Section 11 Direct Memory Access Controller (DMAC) Clock Bus cycle DMAC1 DMAC2 DMAC3 DMAC4 DREQn Blind zone (Active high) ..Acceptance DACKn (Active high) DACK2 DACK1 DACK3 DACK4 RD/WR WEn/DQMxx Figure 11.28 (b) Synchronous DRAM One-Cycle Write Timing Acknowledge Signal Output when External Memory Is Set as DRAM: When external memory is set as DRAM and a row address is output during a read or write, the acknowledge signal is output across the row address and column address (figures 11.29–11.31).
Page 532 Section 11 Direct Memory Access Controller (DMAC) Clock DACKn (Active high) Column address Address DMAC read or write (basic timing) Figure 11.30 DACKn Output in DRAM Burst Accesses (Same Row Address, AM = 0 or 1) Clock DACKn (Active high) Pre- charge address...
Page 533: Dreqn Pin Input Detection Timing
Section 11 Direct Memory Access Controller (DMAC) Acknowledge Signal Output When External Memory Is Set as Burst ROM: When external memory is set as burst ROM, the acknowledge signal is output synchronous to the DMA address (no dual writes allowed) (figure 11.32). Clock DACKn (Active high)
Page 534 Section 11 Direct Memory Access Controller (DMAC) If the DACKn signal is output a number of times, the first DACKn signal for the input DREQn signal indicates the request acceptance start timing, and subsequently each clock edge is sampled. Clock Bus cycle DMAC DMAC...
Page 535 Section 11 Direct Memory Access Controller (DMAC) Clock DMAC DMAC Bus cycle DREQn Blind zone (Active high) acceptance acceptance DACKn (Active high) DACK DACK Figure 11.35 When a16-Bit External Device is Connected (Edge Detection) Clock DMAC DMAC DMAC DMAC Bus cycle DREQn Blind zone Blind zone...
Page 536 Section 11 Direct Memory Access Controller (DMAC) • Cycle-Steal Mode Edge Detection—16-Bit Transfer With 16-byte transfer, the first request signal is the first transfer request, and the second transfer request is accepted when the next request signal is accepted. The third and fourth requests are accepted in the same way.
Page 537 Section 11 Direct Memory Access Controller (DMAC) Clock DMAC Bus cycle DREQn Blind zone Blind zone (Active high) acceptance acceptance DACKn (Active high) Requests acceptable Figure 11.38 DREQn Pin Input Detection Timing in Cycle-Steal Mode with Level Detection (Byte/Word/Longword Setting) Clock DMAC DMAC...
Page 538 Section 11 Direct Memory Access Controller (DMAC) Clock DMAC DMAC DMAC DMAC Bus cycle DREQn Blind zone Blind zone (Active high) acceptance acceptance DACKn (Active high) DACK DACK DACK DACK Figure 11.40 When an 8-Bit External Device is Connected (Level Detection) DREQn Pin Input Detection Timing in Burst Mode: In burst mode, only edge detection is valid for DREQn input.
Page 539: Dma Transfer End
Section 11 Direct Memory Access Controller (DMAC) 11.3.8 DMA Transfer End The DMA transfer ending conditions vary when channels end individually and when both channels end together. Conditions for Channels Ending Individually: When either of the following conditions is met, the transfer will end in the relevant channel only: The DMA transfer count register (TCR) value becomes 0.
Page 540: Bh Pin Output Timing
To use BH, the settings for the CHCR0 register or CHCR1 register in the on-chip DMAC of the SH7616 must be as shown in figure 11.43. BH is not output unless the settings for the CHCR0 register or CHCR1 register are as indicated in figure 11.42.
Page 541 Section 11 Direct Memory Access Controller (DMAC) Bit name — — — — — — — — — — — — — — — — Setting Bit name Setting 16-byte unit (four long words transferred) DMA transfer allowed Source address is incremented Destination address is incremented * Don't care Figure 11.42 Register Settings When Using BH...
Page 542: Usage Examples
Section 11 Direct Memory Access Controller (DMAC) 11.4 Usage Examples 11.4.1 Example of DMA Data Transfer Between SCIF and External Memory In this example data received by the serial communication interface with FIFO (SCIF) is sent to external memory using DMAC channel 1. Table 11.10 lists the transfer conditions and register setting values.
Page 543 Section 11 Direct Memory Access Controller (DMAC) 5. Before changing the frequency or changing to standby mode, set the DME bit of DMAOR to 0 and stop operation of the DMAC. 6. Do not use the DMAC, BSC, UBC, E-DMAC, and EtherC for on-chip peripheral module transfers.
Page 544 Section 11 Direct Memory Access Controller (DMAC) 12. When setting DMAC channel 0 to cycle-steal mode, and channel 1 to cycle-steel mode, dual address mode or built-in peripheral module request, set the priority mode to priority order fixed mode. 13. When SDRAM is connected, set the upper limit of external bus frequency in DMA single address mode transfers to 31.25 MHz.
Page 545: Section 12 16-Bit Free-Running Timer (Frt)
Section 12 16-Bit Free-Running Timer (FRT) Section 12 16-Bit Free-Running Timer (FRT) 12.1 Overview A single-channel, 16-bit free-running timer (FRT) is included on-chip. The FRT is based on a 16-bit free-running counter (FRC) and can output two types of independent waveforms. The FRT can also measure the width of input pulses and the cycle of external clocks.
Page 546: Block Diagram
Section 12 16-Bit Free-Running Timer (FRT) 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the FRT. Internal clock φ/8 φ/32 FTCI φ/128 Clock Clock select OCRA (H/L) Compare match A Comparator A Internal FTOA data bus Overflow FTOB FRC (H/L) Clear Comparator B...
Page 547: Pin Configuration
Section 12 16-Bit Free-Running Timer (FRT) 12.1.3 Pin Configuration Table 12.1 lists FRT I/O pins and their functions. Table 12.1 Pin Configuration Channel Function Counter clock input pin FTCI FRC counter clock input pin Output compare A output pin FTOA Output pin for output compare A Output compare B output pin FTOB...
Page 548: Register Descriptions
Section 12 16-Bit Free-Running Timer (FRT) 12.2 Register Descriptions 12.2.1 Free-Running Counter (FRC) Bit: … … Initial value: … R/W: … FRC is a 16-bit read/write register. It increments upon input of a clock. The input clock can be selected using clock select bits 1 and 0 (CKS1, CKS0) in TCR. FRC can be cleared upon compare match A.
Page 549: Input Capture Register (Ficr)
Section 12 16-Bit Free-Running Timer (FRT) OCR is initialized to H'FFFF by a reset, in standby mode, and when the module standby function is used. 12.2.3 Input Capture Register (FICR) Bit: … … Initial value: … R/W: … FICR is a 16-bit read-only register. When a rising edge or falling edge of the input capture signal (FTI pin) is detected, the current FRC value is transferred to FICR.
Page 550: Free-Running Timer Control/Status Register (Ftcsr)
Section 12 16-Bit Free-Running Timer (FRT) Bits 6 to 4—Reserved: These bits are always read as 0. The write value should always be 0. Bit 3—Output Compare Interrupt A Enable (OCIAE): Selects enabling/disabling of the OCIA interrupt request when the output compare flag A (OCFA) in FTCSR is set to 1. Bit 3: OCIAE Description Interrupt request (OCIA) caused by OCFA disabled...
Page 551 Section 12 16-Bit Free-Running Timer (FRT) Bit 7—Input Capture Flag (ICF): Status flag that indicates that the FRC value has been sent to FICR by the input capture signal. This flag is cleared by software and set by hardware. It cannot be set by software.
Page 552: Timer Control Register (Tcr)
Section 12 16-Bit Free-Running Timer (FRT) Bit 1—Timer Overflow Flag (OVF): Status flag that indicates when FRC overflows (from H'FFFF to H'0000). This flag is cleared by software and set by hardware. It cannot be set by software. Bit 1: OVF Description [Clearing condition] When OVF is read while set to 1, and then 0 is written to it...
Page 553: Timer Output Compare Control Register (Tocr)
Section 12 16-Bit Free-Running Timer (FRT) Bits 1 and 0—Clock Select (CKS1, CKS0): These bits select whether to use an external clock or one of three internal clocks for input to FRC. The external clock is counted at the rising edge. Bit 1: CKS1 Bit 0: CKS0 Description...
Page 554: Cpu Interface
Section 12 16-Bit Free-Running Timer (FRT) Bit 0—Output Level B (OLVLB): Selects the level output to the output compare B output pin upon compare match B (signal indicating match of FRC and OCRB). Bit 0: OLVLB Description 0 output on compare match B (Initial value) 1 output on compare match B 12.3...
Page 555 Section 12 16-Bit Free-Running Timer (FRT) (Write to upper byte) Data bus within module (H'AA) Bus interface upper byte TEMP (H'AA) FRC H FRC L (Write to lower byte) Data bus within module (H'55) Bus interface lower byte TEMP (H'AA) FRC H FRC L (H'AA)
Page 556 Section 12 16-Bit Free-Running Timer (FRT) (Read from upper byte) Data bus within module Bus interface (H'AA) upper byte TEMP (H'55) FRC H FRC L (H'AA) (H'55) (Read from lower byte) Data bus within module (H'55) Bus interface lower byte TEMP (H'AA) FRC H...
Page 557: Operation
Section 12 16-Bit Free-Running Timer (FRT) 12.4 Operation 12.4.1 FRC Count Timing The FRC increments on clock input (internal or external). Internal Clock Operation: Set the CKS1 and CKS0 bits in TCR to select which of the three internal clocks created by dividing system clock φ (φ/8, φ/32, φ/128) is used. Figure 12.4 shows the timing.
Page 558: Output Timing For Output Compare
Section 12 16-Bit Free-Running Timer (FRT) 12.4.2 Output Timing for Output Compare When a compare match occurs, the output level set in the OLVL bit in TOCR is output from the output compare output pins (FTOA, FTOB). Figure 12.6 shows the timing for output of output compare A.
Page 559: Input Capture Input Timing
Section 12 16-Bit Free-Running Timer (FRT) 12.4.4 Input Capture Input Timing Either the rising edge or falling edge can be selected for input capture input using the IEDG bit in TCR. Figure 12.8 shows the timing when the rising edge is selected (IEDG = 1). Pφ...
Page 560: Input Capture Flag (Icf) Setting Timing
Section 12 16-Bit Free-Running Timer (FRT) 12.4.5 Input Capture Flag (ICF) Setting Timing Input capture input sets the input capture flag (ICF) to 1 and simultaneously transfers the FRC value to FICR. Figure 12.10 shows the timing. Pφ Input capture signal FICR Figure 12.10 ICF Setting Timing...
Page 561: Timer Overflow Flag (Ovf) Setting Timing
Section 12 16-Bit Free-Running Timer (FRT) Pφ N + 1 OCRA, OCRB Compare match signal OCFA, OCFB Figure 12.11 OCF Setting Timing 12.4.7 Timer Overflow Flag (OVF) Setting Timing FRC overflow (from H'FFFF to H'0000) sets the timer overflow flag (OVF) to 1. Figure 12.12 shows the timing.
Page 562: Interrupt Sources
Section 12 16-Bit Free-Running Timer (FRT) 12.5 Interrupt Sources There are four FRT interrupt sources of three types (ICI, OCIA/OCIB, and OVI). Table 12.3 lists the interrupt sources and their priorities after a reset is cleared. The interrupt enable bits in TIER are used to enable or disable the interrupt bits.
Page 563: Usage Notes
Section 12 16-Bit Free-Running Timer (FRT) 12.7 Usage Notes Note that the following contention and operations occur when the FRT is operating: 12.7.1 Contention between FRC Write and Clear When a counter clear signal is generated with the timing shown in figure 12.14 during the write cycle for the lower byte of FRC, writing does not occur to the FRC, and the FRC clear takes priority.
Page 564: Contention Between Frc Write And Increment
Section 12 16-Bit Free-Running Timer (FRT) 12.7.2 Contention between FRC Write and Increment When an increment occurs with the timing shown in figure 12.15 during the write cycle for the lower byte of FRC, no increment is performed and the counter write takes priority. FRC lower-byte write cycle Pφ...
Page 565: Contention Between Ocr Write And Compare Match
Section 12 16-Bit Free-Running Timer (FRT) 12.7.3 Contention between OCR Write and Compare Match When a compare match occurs with the timing shown in figure 12.16, during the write cycle for the lower byte of OCRA or OCRB, the OCR write takes priority and the compare match signal is disabled.
Page 566: Internal Clock Switching And Counter Operation
Section 12 16-Bit Free-Running Timer (FRT) 12.7.4 Internal Clock Switching and Counter Operation FRC will sometimes begin incrementing because of the timing of switching between internal clocks. Table 12.4 shows the relationship between internal clock switching timing (CKS1 and CKS0 bit rewrites) and FRC operation. When an internal clock is used, the FRC clock is generated when the falling edge of an internal clock (created by dividing the system clock (φ)) is detected.
Page 567: Timer Output (Ftoa, Ftob)
Section 12 16-Bit Free-Running Timer (FRT) Timing of Rewrite of CKS1 and CKS0 Bits FRC Operation High-to-low switch Clock before switching Clock after switching FRC clock N + 1 N + 2 Rewrite of CKS bit High-to-high switch Clock before switching Clock after switching...
Page 568 Section 12 16-Bit Free-Running Timer (FRT) Rev. 2.00 Mar 09, 2006 page 542 of 906 REJ09B0292-0200...
Page 569: Section 13 Watchdog Timer (Wdt)
Section 13 Watchdog Timer (WDT) Section 13 Watchdog Timer (WDT) 13.1 Overview A single-channel watchdog timer (WDT) is provided on-chip for monitoring system operations. If a system becomes uncontrolled and the timer counter overflows without being rewritten correctly by the CPU, an overflow signal (WDTOVF) is output externally. The WDT can simultaneously generate an internal reset signal for the entire chip.
Page 570: Block Diagram
Section 13 Watchdog Timer (WDT) 13.1.2 Block Diagram Figure 13.1 shows a block diagram of the WDT. φ/4 Overflow φ/128 Interrupt (Interrupt control φ/256 request signal) φ/512 Clock Clock φ/1024 select φ/2048 φ/8192 WDTOVF Reset φ/16384 Internal control reset signal* Internal clock RSTCSR...
Page 571: Register Configuration
Section 13 Watchdog Timer (WDT) 13.1.4 Register Configuration Table 13.2 summarizes the three WDT registers. They are used to select the clock, switch the WDT mode, and control the reset signal. Table 13.2 Register Configuration Address Write * Read * Name Abbreviation R/W Initial Value...
Page 572: Watchdog Timer Control/Status Register (Wtcsr)
Section 13 Watchdog Timer (WDT) 13.2.2 Watchdog Timer Control/Status Register (WTCSR) Bit: WT/IT — — CKS2 CKS1 CKS0 Initial value: R/(W) * R/W: Note: * Only 0 can be written in bit 7, to clear the flag. The watchdog timer control/status register (WTCSR) is an 8-bit read/write register. The method of writing to WTCSR differs from that of most other registers to prevent inadvertent rewriting.
Page 573: Reset Control/Status Register (Rstcsr)
Section 13 Watchdog Timer (WDT) Bit 5—Timer Enable (TME): Enables or disables the timer. Bit 5: TME Description Timer disabled: WTCNT is initialized to H'00 and count-up stops (Initial value) Timer enabled: WTCNT starts counting. A WDTOVF signal or interrupt is generated when WTCNT overflows Bits 4 and 3—Reserved: These bits are always read as 1.
Page 574 Section 13 Watchdog Timer (WDT) of writing to RSTCSR differs from that of most other registers to prevent inadvertent rewriting. See section 13.2.4, Notes on Register Access, for details. RSTCR is initialized to H'1D by input of a reset signal from the RES pin, but is not initialized by the internal reset signal generated by overflow of the WDT.
Page 575: Notes On Register Access
Section 13 Watchdog Timer (WDT) 13.2.4 Notes on Register Access The watchdog timer’s WTCNT, WTCSR, and RSTCSR registers differ from other registers in that they are more difficult to write. The procedures for writing and reading these registers are given below.
Page 576: Operation
Section 13 Watchdog Timer (WDT) Writing 0 to the WOVF bit Address: H'FFFFFE82 H'A5 H'00 Writing to the RSTE and RSTS bits Address: H'FFFFFE82 H'5A Write data Figure 13.3 Writing to RSTCSR Reading from WTCNT, WTCSR, and RSTCSR: WTCNT, WTCSR, and RSTCSR are read like other registers.
Page 577 Section 13 Watchdog Timer (WDT) WTCNT value Overflow H'FF H'00 Time WT/IT = 1 H'00 written WOVF = 1 WT/IT = 1 H'00 written TME = 1 in WTCNT TME = 1 in WTCNT WDTOVF and internal reset generated WDTOVF signal 512 φ...
Page 578: Operation In Interval Timer Mode
Section 13 Watchdog Timer (WDT) 13.3.2 Operation in Interval Timer Mode To use the WDT as an interval timer, clear WT/IT to 0 and set TME to 1 in WTCSR. An interval timer interrupt (ITI) is generated each time the watchdog timer counter (WTCNT) overflows. This function can be used to generate interval timer interrupts at regular intervals (figure 13.5).
Page 579: Timing Of Overflow Flag (Ovf) Setting
Section 13 Watchdog Timer (WDT) 13.3.4 Timing of Overflow Flag (OVF) Setting In interval timer mode, when WTCNT overflows, the OVF flag in WTCSR is set to 1 and an interval timer interrupt (ITI) is requested (figure 13.6). WTCNT H'FF H'00 Overflow signal (internal signal)
Page 580: Usage Notes
Section 13 Watchdog Timer (WDT) 13.4 Usage Notes 13.4.1 Contention between WTCNT Write and Increment If a count-up pulse is generated at the timing shown in figure 13.8 during a watchdog timer counter (WTCNT) write cycle, the write takes priority and the timer counter is not incremented (figure 13.8).
Page 581: System Reset With Wdtovf
Section 13 Watchdog Timer (WDT) System Reset with WDTOVF WDTOVF WDTOVF WDTOVF 13.4.4 If a WDTOVF signal is input to the RES pin, the device cannot initialize correctly. Avoid logical input of the WDTOVF output signal to the RES input pin. To reset the entire system with the WDTOVF signal, use the circuit shown in figure 13.9.
Page 582 Section 13 Watchdog Timer (WDT) Rev. 2.00 Mar 09, 2006 page 556 of 906 REJ09B0292-0200...
Page 583: Section 14 Serial Communication Interface With Fifo (Scif)
14.1 Overview The SH7616 is equipped with a two-channel serial communication interface with built-in FIFO buffers (SCIF: SCI with FIFO). The SCIF can handle both asynchronous and synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function).
Page 584 Section 14 Serial Communication Interface with FIFO (SCIF)  Synchronous mode Serial data communication is synchronized with a clock. Serial data communication can be carried out with other chips that have a synchronous communication function. There is a single serial data communication format. •...
Page 585: Block Diagrams
Section 14 Serial Communication Interface with FIFO (SCIF) 14.1.2 Block Diagrams A block diagram of the SCIF is shown in figure 14.1, and a diagram of the IrDA block in figure 14.2. Module data bus Internal data bus SCFRDR SCFTDR SCFDR SCBRR (16-stage)
Page 586: Pin Configuration
Section 14 Serial Communication Interface with FIFO (SCIF) Clock input Modulation unit Transmit clock SCIF Demodulation unit IrDA IrDA/SCIF switchover Figure 14.2 Diagram of IrDA Block 14.1.3 Pin Configuration The SCIF has the serial pins shown in table 14.1. Table 14.1 SCIF Pins Channel Name Abbreviation...
Page 587: Register Configuration
Section 14 Serial Communication Interface with FIFO (SCIF) 14.1.4 Register Configuration The SCIF has the internal registers shown in table 14.2. These registers are used to specify asynchronous mode/synchronous mode and the IrDA communication mode, the data format and the bit rate, and to perform transmitter/receiver control. Table 14.2 SCIF Registers Abbre- Initial...
Page 588: Register Descriptions
Section 14 Serial Communication Interface with FIFO (SCIF) 14.2 Register Descriptions With the exception of the IrDA mode register (SCIMR) and bits 6 to 3 (ICK3 to ICK0) of the serial mode register (SCSMR), IrDA communication mode settings are the same as for asynchronous mode.
Page 589: Transmit Shift Register (Sctsr)
Section 14 Serial Communication Interface with FIFO (SCIF) 14.2.3 Transmit Shift Register (SCTSR) Bit: R/W: — — — — — — — — The transmit shift register (SCTSR) is the register used to transmit serial data. To perform serial data transmission, the SCIF first transfers transmit data from SCFTDR to SCTSR, then sends the data to the TxD pin starting with the LSB (bit 0) or MSB (bit 7).
Page 590: Serial Mode Register (Scsmr)
Section 14 Serial Communication Interface with FIFO (SCIF) 14.2.5 Serial Mode Register (SCSMR) Bit: CHR/ O/E/ STOP/ CKS1 CKS0 ICK3 ICK2 ICK1 ICK0 Initial value: R/W: The serial mode register (SCSMR) is an 8-bit register used to set the SCIF’s serial communication format and select the baud rate generator clock source.
Page 591 Section 14 Serial Communication Interface with FIFO (SCIF) Bit 5—Parity Enable (PE)/IrDA Clock Select 2 (ICK2): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In synchronous mode, parity bit addition and checking is not performed, regardless of the PE bit setting.
Page 592 Section 14 Serial Communication Interface with FIFO (SCIF) Bit 3—Stop Bit Length (STOP)/IrDA Clock Select 0 (ICK0): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bit setting is only valid in asynchronous mode. When synchronous mode is set, the STOP bit setting is invalid since stop bits are not added.
Page 593: Serial Control Register (Scscr)
Section 14 Serial Communication Interface with FIFO (SCIF) For the relationship between the clock source, the bit rate register setting, and the baud rate, see section 14.2.9, Bit Rate Register (SCBRR). Bit 1: Bit 0: CKS1 CKS0 Description Pφ clock (Initial value) Pφ/4 clock Pφ/16 clock...
Page 594 Section 14 Serial Communication Interface with FIFO (SCIF) Bit 6—Receive Interrupt Enable (RIE): Enables or disables generation of a receive-FIFO-data-full interrupt (RXI) request and receive-error interrupt (ERI) request when, after serial receive data is transferred from the receive shift register (SCRSR) to the receive FIFO data register (SCFRDR), the number of data bytes in SCFRDR reaches or exceeds the receive trigger set number, and the RDF flag is set to 1 in SC1SSR.
Page 595 Section 14 Serial Communication Interface with FIFO (SCIF) Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when the MP bit in SCSMR is set to 1. The MPIE bit setting is invalid in synchronous mode and IrDA mode, and when the MP bit is 0. Bit 3: MPIE Description Multiprocessor interrupts disabled (normal reception performed) (Initial value)
Page 596: Serial Status 1 Register (Sc1Ssr)
Section 14 Serial Communication Interface with FIFO (SCIF) Bit 1: Bit 0: CKE1 CKE0 Description Asynchronous mode Internal clock/SCK pin functions as input pin (input signal ignored) * Synchronous mode Internal clock/SCK pin functions as serial clock output * Internal clock/SCK pin functions as clock output * Asynchronous mode Synchronous mode Internal clock/SCK pin functions as serial clock...
Page 597 Section 14 Serial Communication Interface with FIFO (SCIF) SC1SSR is initialized to H'0084 by a reset, by the module standby function, and in standby mode. Bits 15 to 12—Parity Error Count 3 to 0 (PER3 to PER0): These bits indicate the number of data bytes in which a parity error occurred in the receive data in the receive FIFO data register.
Page 598 Section 14 Serial Communication Interface with FIFO (SCIF) Bit 6—Transmit End (TEND): Indicates that there is no valid data in SCFTDR when the last bit of the transmit character is sent, and transmission has been ended. Bit 6: TEND Description Transmission is in progress [Clearing condition] When data is written to SCFTDR while TE = 1...
Page 599 Section 14 Serial Communication Interface with FIFO (SCIF) Bit 4—Break Detect (BRK): Indicates that a receive data break signal has been detected. Bit 4: BRK Description A break signal has not been received (Initial value) [Clearing conditions] • In a reset or in standby mode •...
Page 600 Section 14 Serial Communication Interface with FIFO (SCIF) Bit 1—Receive Data Register Full (RDF): Indicates that the received data has been transferred to the receive FIFO data register (SCFRDR), and the number of receive data bytes in SCFRDR is equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control register (SCFCR).
Page 601: Serial Status 2 Register (Sc2Ssr)
Section 14 Serial Communication Interface with FIFO (SCIF) Bit 0—Receive Data Ready (DR): Indicates that there are fewer than the receive trigger set number of data bytes in the receive FIFO data register (SCFRDR), and no further data has arrived for at least 16 etu after the stop bit of the last data received.
Page 602 Section 14 Serial Communication Interface with FIFO (SCIF) Bit 7—Transmit LSB/MSB-First Select (TLM): Selects LSB-first or MSB-first mode in data transmission. Bit 7: TLM Description LSB-first transmission (Initial value) MSB-first transmission Bit 6—Receive LSB/MSB-First Select (RLM): Selects LSB-first or MSB-first mode in data reception.
Page 603 Section 14 Serial Communication Interface with FIFO (SCIF) The MPBT bit setting is invalid in synchronous mode and IrDA mode, when a multiprocessor format is not used, and when the operation is not transmission. Bit 2: MPBT Description Data with a 0 multiprocessor bit is transmitted (Initial value) Data with a 1 multiprocessor bit is transmitted Bit 1—Receive Data Error Ignore Enable (EI): Selects whether or not the receive operation is to...
Page 604: Bit Rate Register (Scbrr)
Section 14 Serial Communication Interface with FIFO (SCIF) 14.2.9 Bit Rate Register (SCBRR) Bit: Initial value: R/W: The bit rate register (SCBRR) is an 8-bit register that sets the serial transmit/receive bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in the serial mode register (SCSMR).
Page 605 Section 14 Serial Communication Interface with FIFO (SCIF) SCSMR Settings Clock CKS1 CKS0 Pφ Pφ/4 Pφ/16 Pφ/64 The bit rate error in asynchronous mode is found from the following equations: Pφ × 10 – 1 × 100 Error (%) = (N + 1) ×...
Page 606 Section 14 Serial Communication Interface with FIFO (SCIF) Table 14.3 Examples of Bit Rates and SCBRR Settings in Asynchronous Mode Pφ φ φ φ (MHz) 2.097152 2.4576 Bit Rate Error Error Error Error (Bits/s) 0.03 –0.04 –0.26 0.03 0.16 0.21 0.00 0.16 0.16...
Page 607 Section 14 Serial Communication Interface with FIFO (SCIF) Pφ φ φ φ (MHz) 6.144 7.37288 Bit Rate Error Error Error Error (Bits/s) –0.44 0.08 –0.07 0.03 0.16 0.00 0.00 0.16 0.16 0.00 0.00 0.16 0.16 0.00 0.00 0.16 1200 0.16 0.00 0.00 0.16...
Page 608 Section 14 Serial Communication Interface with FIFO (SCIF) Pφ φ φ φ (MHz) 14.7456 Bit Rate Error Error Error (Bits/s) 0.70 0.03 0.13 0.00 0.16 –0.35 0.00 0.16 0.16 0.00 0.16 –0.35 1200 0.00 0.16 0.16 2400 0.00 0.16 –0.35 4800 0.00 0.16...
Page 609 Section 14 Serial Communication Interface with FIFO (SCIF) Table 14.4 Examples of Bit Rates and SCBRR Settings in Synchronous Mode Pφ φ φ φ (MHz) Bit Rate (Bits/s) — — — — — — — — — — 2.5 k 10 k 25 k 50 k...
Page 610 Section 14 Serial Communication Interface with FIFO (SCIF) Table 14.5 shows the maximum bit rate for various frequencies in asynchronous mode when using the baud rate generator. Tables 14.6 and 14.7 show the maximum bit rates when using external clock input. Table 14.5 Maximum Bit Rate for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings...
Page 611 Section 14 Serial Communication Interface with FIFO (SCIF) Table 14.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) Pφ φ φ φ (MHz) External Input Clock (MHz) Maximum Bit Rate (Bits/s) 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 0.7500 46875 3.6864...
Page 612: Fifo Control Register (Scfcr)
Section 14 Serial Communication Interface with FIFO (SCIF) 14.2.10 FIFO Control Register (SCFCR) Bit: RTRG1 RTRG0 TTRG1 TTRG0 TFRST RFRST LOOP Initial value: R/W: The FIFO control register (SCFCR) performs data count resetting and trigger data number setting for the transmit and receive FIFO registers, and also contains a loopback test enable bit. SCFCR can be read or written to at all times.
Page 613 Section 14 Serial Communication Interface with FIFO (SCIF) Bit 3—Modem Control Enable (MCE): Enables or disables the CTS and RTS modem control signals. Bit 3: MCE Description Modem signals disabled * (Initial value) Modem signals enabled Note: * CTS is fixed at active-0 regardless of the input value, and RTS output is also fixed at 0. Bit 2—Transmit FIFO Data Register Reset (TFRST): Invalidates the transmit data in the transmit FIFO data register and resets it to the empty state.
Page 614: Fifo Data Count Register (Scfdr)
Section 14 Serial Communication Interface with FIFO (SCIF) 14.2.11 FIFO Data Count Register (SCFDR) The FIFO data count register (SCFDR) is a 16-bit register that indicates the number of data bytes stored in the transmit FIFO data register (SCFTDR) and receive FIFO data register (SCFRDR). The upper 8 bits show the number of transmit data bytes in SCFTDR, and the lower 8 bits show the number of receive data bytes in SCFRDR.
Page 615: Fifo Error Register (Scfer)
Section 14 Serial Communication Interface with FIFO (SCIF) 14.2.12 FIFO Error Register (SCFER) The FIFO error register (SCFER) indicates the data location at which a parity error or framing error occurred in receive data stored in the receive FIFO data register (SCFRDR). SCFER can be read at all times.
Page 616 Section 14 Serial Communication Interface with FIFO (SCIF) Bit: IRMOD PSEL RIVS — — — — — Initial value: R/W: Bit 7—IrDA Mode (IRMOD): Selects operation as an IrDA serial communication interface. Bit 7: IRMOD Description Operation as SCIF is selected (Initial value) Operation as IrDA is selected * Note: * When operation as an IrDA interface is selected, bit 7 (C/A) of the serial mode register...
Page 617: Operation
Section 14 Serial Communication Interface with FIFO (SCIF) 14.3 Operation 14.3.1 Overview The SCIF can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. An IrDA block is also provided, enabling infrared communication conforming to IrDA 1.0 to be executed by connecting an infrared transmission/reception unit.
Page 618 Section 14 Serial Communication Interface with FIFO (SCIF) When external clock is selected: The on-chip baud rate generator is not used, and the SCIF operates on the input serial clock. • IrDA Mode  IrDA 1.0 compliance  Data length: 8 bits ...
Page 619: Operation In Asynchronous Mode
Section 14 Serial Communication Interface with FIFO (SCIF) Table 14.9 SCSMR and SCSCR Settings for SCIF Clock Source Selection SCSMR SCSCR Setting SCIF Transmit/Receive Clock Bit 7: Bit 1: Bit 0: Clock C/A A A A CKE1 CKE0 Mode Source SCK Pin Function Asynchronous Internal...
Page 620 Section 14 Serial Communication Interface with FIFO (SCIF) In asynchronous mode, the SCIF performs synchronization at the falling edge of the start bit in reception. The SCIF samples the data on the eighth (fourth, second) pulse of a clock with a frequency of 16 (8, 4) times the length of one bit, so that the transfer data is latched at the center of each bit.
Page 621 Section 14 Serial Communication Interface with FIFO (SCIF) Table 14.10 Serial Transmit/Receive Formats (Asynchronous Mode) SCSMR Settings Serial Transmit/Receive Format and Frame Length CHR PE MP STOP 8-bit data STOP 8-bit data STOP STOP 8-bit data STOP 8-bit data STOP STOP 8-bit data STOP 8-bit data...
Page 622 Section 14 Serial Communication Interface with FIFO (SCIF) Clock: Either an internal clock generated by the built-in baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR.
Page 623 Section 14 Serial Communication Interface with FIFO (SCIF) 1. Set the clock selection in SCSCR. Initialization Be sure to clear bits RIE, TIE, and MPIE, and bits TE and RE, to 0. When clock output is selected in Clear TE and RE bits asynchronous mode, it is output to 0 in SCSCR immediately after SCSCR settings are...
Page 624 Section 14 Serial Communication Interface with FIFO (SCIF) 1. PFC initialization: Set the TxD pin, and Initialization the SCK pin if necessary, with the PFC. 2. SCIF status check and transmit data Start of transmission write: Read the serial status 1 register (SC1SSR) and check that the TDFE bit is set to 1, then write transmit data to the Read TDFE bit in SC1SSR...
Page 625 Section 14 Serial Communication Interface with FIFO (SCIF) In serial transmission, the SCIF operates as described below. 1. When data is written to the transmit FIFO data register (SCFTDR), the SCIF transfers the data to the transmit shift register (SCTSR), and starts transmitting. Check that the TDFE flag is set to 1 in the serial status 1 register (SC1SSR) before writing transmit data to SCFTDR.
Page 626 Section 14 Serial Communication Interface with FIFO (SCIF) Start Data Parity Stop Start Data Parity Stop Serial Idle state data (mark state) TDFE TEND TXI interrupt TXI interrupt request request Data written to SCFTDR and TDFE flag cleared to 0 by TXI interrupt handler One frame Figure 14.6 Example of Transmit Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit, LSB-First Transfer)
Page 627 Section 14 Serial Communication Interface with FIFO (SCIF) • Serial Data Reception (Asynchronous Mode) Figure 14.8 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. 1. PFC initialization: Set the RxD pin, and Initialization the SCK pin if necessary, with the PFC.
Page 628 Section 14 Serial Communication Interface with FIFO (SCIF) 1. Whether a framing error or Error handling parity error has occurred in the receive data read from SCFRDR can be ascertained ORER = 1? from the FER and PER bits in SC1SSR.
Page 629 Section 14 Serial Communication Interface with FIFO (SCIF) In serial reception, the SCIF operates as described below. 1. The SCIF monitors the communication line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR in LSB-to-MSB order or MSB-to-LSB order according to the setting of the RLM bit in SC2SSR.
Page 630 Section 14 Serial Communication Interface with FIFO (SCIF) Table 14.11 Receive Error Conditions Receive Error Abbreviation Condition Data Transfer Overrun error ORER Next serial receive operation is Receive data is not transferred completed while there are 16 from SCRSR to SCFRDR receive data bytes in SCFRDR Framing error Stop bit is 0...
Page 631: Multiprocessor Communication Function
Section 14 Serial Communication Interface with FIFO (SCIF) Start Parity Start Serial data RTS) Figure 14.10 Example of Operation Using Modem Control (RTS 14.3.3 Multiprocessor Communication Function The multiprocessor communication function performs serial communication using a multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode.
Page 632 Section 14 Serial Communication Interface with FIFO (SCIF) Transmitting station Serial communication line Receiving Receiving Receiving Receiving station A station B station C station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial H'01 H'AA data (MPB = 1) (MPB = 0)
Page 633 Section 14 Serial Communication Interface with FIFO (SCIF) 1. PFC initialization: Set the TxD pin, and Initialization the SCK pin if necessary, with the PFC. 2. SCIF status check and transmit data Start of transmission write: Read the serial status 1 register (SC1SSR) and check that the TDFE bit is set to 1, then write transmit data to Read TDFE bit in SC1SSR...
Page 634 Section 14 Serial Communication Interface with FIFO (SCIF) In serial transmission, the SCIF operates as described below. 1. When data is written to SCFTDR, the SCIF transfers the data to SCTSR and starts transmitting. Check that the TDFE flag is set to 1 in SC1SSR before writing transmit data to SCFTDR.
Page 635 Section 14 Serial Communication Interface with FIFO (SCIF) Multi- Multi- Start Data proces- Stop Start proces- Stop sor bit sor bit Serial Idle state data (mark state) TDFE TEND TXI interrupt TXI interrupt request request Data written to SCFTDR and TDFE flag cleared to 0 by TXI interrupt handler One frame Figure 14.13 Example of SCIF Transmit Operation...
Page 636 Section 14 Serial Communication Interface with FIFO (SCIF) 1. PFC initialization: Set the RxD pin, Initialization and the SCK pin if necessary, with the PFC. Start of reception 2. ID reception cycle: Set the MPIE bit to 1 in SCSCR. Set MPIE bit to 1 in SCSCR 3.
Page 637 Section 14 Serial Communication Interface with FIFO (SCIF) 1. Whether a framing error has Error handling occurred in the receive data read from SCFRDR can be ascertained from the FER bit in SC1SSR. ORER = 1? 2. When a break signal is received, receive data is not transferred to SCFRDR while the BRK flag is set.
Page 638 Section 14 Serial Communication Interface with FIFO (SCIF) Figure 14.15 shows an example of SCIF operation for multiprocessor format reception. Start Stop Start Stop Data (ID1) Data (Data1) Serial Idle state data (mark state) MPIE SCFRDR value RXI interrupt request SCFRDR data read As data is not this RXI interrupt request...
Page 639: Operation In Synchronous Mode
Section 14 Serial Communication Interface with FIFO (SCIF) 14.3.4 Operation in Synchronous Mode In synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCIF, the transmitter and receiver are independent units, enabling full-duplex communication using a common clock.
Page 640 Section 14 Serial Communication Interface with FIFO (SCIF) Transmit/Receive Format: A fixed 8-bit data format is used. No parity or multiprocessor bits are added. Clock: Either an internal clock generated by the built-in baud rate generator or an external serial clock input at the SCK pin can be selected, according to the setting of the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR.
Page 641 Section 14 Serial Communication Interface with FIFO (SCIF) 1. Set the clock selection in SCSCR. Initialization Be sure to clear bits RIE, TIE, MPIE, TE, and RE to 0. Clear TE and RE bits to 0 2. Set the transmit/receive format in in SCSCR the serial mode register (SCSMR).
Page 642 Section 14 Serial Communication Interface with FIFO (SCIF) • Serial Data Transmission (Synchronous Mode) Figure 14.18 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission. 1. PFC initialization: Set the TxD pin, Initialization and the SCK pin if necessary, with the PFC.
Page 643 Section 14 Serial Communication Interface with FIFO (SCIF) In serial transmission, the SCIF operates as described below. 1. When data is written to the transmit FIFO data register (SCFTDR), the SCIF transfers the data from SCFTDR to the transmit shift register (SCTSR), and starts transmitting. Check that the TDFE flag is set to 1 in the serial status 1 register (SC1SSR) before writing transmit data to SCFTDR.
Page 644 Section 14 Serial Communication Interface with FIFO (SCIF) Transfer direction Serial clock Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Serial data TDFE TEND TXI interrupt TXI interrupt Data written to SCFTDR request request and TDFE flag cleared to 0 by TXI interrupt handler...
Page 645 Section 14 Serial Communication Interface with FIFO (SCIF) 1. PFC initialization: Set the RxD pin, Initialization and the SCK pin if necessary, with the PFC. Start of reception 2. Receive error handling: If a receive error occurs, read the ORER flag in SC2SSR, and after performing the appropriate error Read ORER flag in SC2SSR handling, clear the ORER flag to...
Page 646 Section 14 Serial Communication Interface with FIFO (SCIF) Error handling ORER = 1? Overrun error handling Clear ORER flag to 0 in SC2SSR Figure 14.20 Sample Serial Reception Flowchart (2) In serial reception, the SCIF operates as described below. 1. The SCIF performs internal initialization in synchronization with serial clock input or output. 2.
Page 647 Section 14 Serial Communication Interface with FIFO (SCIF) Transfer direction Serial clock Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Serial data ORER RXI interrupt Data read from SCFRDR RXI interrupt ERI interrupt request and RDF flag cleared to 0 request request due...
Page 648 Section 14 Serial Communication Interface with FIFO (SCIF) 1. PFC initialization: Set the TxD and Initialization RxD pins, and the SCK pin if necessary, with the PFC. Start of transmission/ 2. SCIF status check and transmit data reception write: Read SC1SSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR and clear Read TDFE flag in SC1SSR...
Page 649: Use Of Transmit/Receive Fifo Buffers
Section 14 Serial Communication Interface with FIFO (SCIF) 14.3.5 Use of Transmit/Receive FIFO Buffers The SCIF has independent 16-stage FIFO buffers for transmission and reception. The configuration of these buffers is shown in figure 14.23. SCTSR SCRSR SCFTDR SCFRDR 1st stage 1st stage Error 2nd stage...
Page 650 Section 14 Serial Communication Interface with FIFO (SCIF) In Serial Data Transmit Operations: In transmission, when transmit data is written to the transmit FIFO by the CPU or DMAC and the TE bit is set to 1 in the serial control register (SCSCR), the data is first transferred to the transmit shift register (SCTSR) in the order of writing to the transmit FIFO, a parity bit is added by the parity generator (P/G), and then serial data is transmitted from the TxD pin.
Page 651 Section 14 Serial Communication Interface with FIFO (SCIF) • Receive FIFO Control in Error Data Reception When data is transferred from SCRSR to the receive FIFO, the P and F flags are also transferred. If either of these flags is set to 1, the error counter is incremented and the corresponding bit (PER3 to PER0, FER3 to FER0) is updated in the serial status 1 register (SC1SSR).
Page 652: Operation In Irda Mode
Section 14 Serial Communication Interface with FIFO (SCIF) 14.3.6 Operation in IrDA Mode In IrDA mode, the waveform of TxD/RxD transmit/receive data is modified to comply with the IrDA 1.0 infrared communication specification. This makes it possible to carry out infrared transmission and reception conforming to the IrDA 1.0 standard by connecting an infrared transmission/reception transceiver/receiver.
Page 653 Section 14 Serial Communication Interface with FIFO (SCIF) UART frame Start bit Stop bit Data Transmission Reception IR frame Start bit Stop bit Data 3/16 bit cycle pulse width Bit cycle Figure 14.24 IrDA Mode Transmit/Receive Operations Pulse Width Selection: In transmission, the IR frame pulse width can be selected as either 3/16 of the transmission bit rate or a smaller pulse width by means of the PSEL bit in the IrDA mode register (SCIMR).
Page 654 Section 14 Serial Communication Interface with FIFO (SCIF) The minimum IR frame pulse width must be 3/16 of the 115.2 kbps bit rate (= 1.63 µsec). With this minimum pulse width, IRCLK = 921.6 kHz, and so the setting for bits ICK3 to ICK0 to give the minimum settable pulse width is given by the following equation.
Page 655 Section 14 Serial Communication Interface with FIFO (SCIF) Table 14.12 Bits ICK3 to ICK0 and Operating Frequencies in IrDA mode (When PSEL = 1) Setting of Bits ICK3 to ICK0 in SCSMR Operating Frequency Pφ φ φ φ (MHz) ICK3 ICK2 ICK1 ICK0...
Page 656: Scif Interrupt Sources And The Dmac
Section 14 Serial Communication Interface with FIFO (SCIF) 14.4 SCIF Interrupt Sources and the DMAC The SCIF has four interrupt sources: the break interrupt (BRI) request, receive-error interrupt (ERI) request, receive-FIFO-data-full interrupt (RXI) request, and transmit-FIFO-data-empty interrupt (TXI) request. Table 14.13 shows the interrupt sources and their relative priorities. The interrupt sources can be enabled or disabled with the TIE or RIE bit in SCSCR.
Page 657: Usage Notes
Section 14 Serial Communication Interface with FIFO (SCIF) 14.5 Usage Notes The following points should be noted when using the SCIF. SCFTDR Writing and the TDFE Flag: The TDFE flag in the serial status 1 register (SC1SSR) is set when the number of transmit data bytes written in the transmit FIFO data register (SCFTDR) has fallen to or below the transmit trigger number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR).
Page 658 Section 14 Serial Communication Interface with FIFO (SCIF) Break Detection and Processing: Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set.
Page 659 Section 14 Serial Communication Interface with FIFO (SCIF) 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 Base clock –7.5 clocks +7.5 clocks...
Page 660 Section 14 Serial Communication Interface with FIFO (SCIF) • In reception, note that if RE is cleared to 0 from 2.3 to 3.5 peripheral operating clock cycles after the rising edge of the RxD D7 bit SCK input, RDF will be set to 1 but copying to SCFRDR will not be possible.
Page 661 Section 14 Serial Communication Interface with FIFO (SCIF) The number of receive data bytes in SCFRDR can be found from the lower 8 bits of the FIFO data count register (SCFDR). SCFRDR Reading when Overrun Occurs: If a receive operation is continued despite the fact that the receive FIFO data register (SCFRDR) contains 16 bytes of data, overrun will occur.
Page 662 Section 14 Serial Communication Interface with FIFO (SCIF) Rev. 2.00 Mar 09, 2006 page 636 of 906 REJ09B0292-0200...
Page 663: Section 15 Serial I/O With Fifo (Siof)
Section 15 Serial I/O with FIFO (SIOF) Section 15 Serial I/O with FIFO (SIOF) 15.1 Overview The serial I/O with FIFO functions mainly as an interface between the chip and a codec or modem analog front-end. 15.1.1 Features The serial I/O has the following features: •...
Page 664 Section 15 Serial I/O with FIFO (SIOF) 16bits Peripheral bus SISTR SICTR SIFCR SIRDR SITDR SIFDR SIRCDR SITCDR Bit counter I/O control unit MSB/LSB selector Conversion circuit MSB/LSB Conversion circuit SIRSR SITSR Serial I/O with FIFO module (SIOF) SRXD SRCK SRS STS STCK STXD...
Page 665: Register Configuration
Section 15 Serial I/O with FIFO (SIOF) 15.2 Register Configuration Table 15.2 shows the SIOF’s registers. Table 15.2 Register Configuration Initial Register Abbreviation Value Address Access Size (Bits) Receive shift register SIRSR0 — — — — Receive data register SIRDR0 H'FFFFFC00 8, 16, 32 specified...
Page 666: Receive Data Register (Sirdr)
Section 15 Serial I/O with FIFO (SIOF) When transfer of control data to SIRSR is completed, the data contents are automatically transferred to the receive control data register (SIRCDR), and the receive control data register full flag (RCD) is set in SISTR. If the next data word input operation ends before the RDRF flag is cleared, an overrun error occurs, the receive overrun error flag (RERR) is set in SISTR, and an overrun error signal is sent to the interrupt controller (INTC).
Page 667: Transmit Shift Register (Sitsr)
Section 15 Serial I/O with FIFO (SIOF) 15.2.3 Transmit Shift Register (SITSR) Bit: Initial value: — — — — — — — R/W: — — — — — — — SITSR is a 16-bit register used to transmit serial data. The contents of this register are shifted in MSB-first or LSB-first order, based on the LM bit in SIFCR, in synchronization with the rising edge of the serial transmit clock (STCK), and output from the serial transmit data STXD pin.
Page 668: Serial Control Register (Sictr)
Section 15 Serial I/O with FIFO (SIOF) with a value less than or equal to the setting of TFWM3 to TFWM0 in SIFCR is transferred from SITDR to SITSR, TDRE is set in SISTR. If at this point the transmit interrupt enable flag (TIE) is set, a transmit-data-empty interrupt (TDEI) request is sent to the INTC and DMAC.
Page 669 Section 15 Serial I/O with FIFO (SIOF) Clear this bit to 0 if SIRCDR and SITCDR are not used, or if all interrupts triggered by the RDRF, TDRE, RCD and TCD bits in SISTR are to be processed by the CPU. The initial value of this bit is 0.
Page 670 Section 15 Serial I/O with FIFO (SIOF) Bit 5—Synchronization Signal Enable (SE): Specifies whether the synchronization signals are to be used for all serial data transfers, or only for the first transfer. When this bit is cleared to 0, the synchronization signals (SRS and STS) are necessary only for the first data transfer, and are not required for subsequent transfers.
Page 671: Serial Status Register (Sistr)
Section 15 Serial I/O with FIFO (SIOF) Bit 1—Enables data transmission. When this flag is cleared, the STXD pin goes to the high- impedance state. When TM is set to 1, the STS pin also goes to the high-impedance state. Bit 1: TE Description Transmission disabled: STxD pin goes to high-impedance state (Initial value)
Page 672 Section 15 Serial I/O with FIFO (SIOF) Bit 9—Transmit Control Data Register Empty (TCD): This flag indicates when SITCDR is empty and can be written to. Bit 9: TCD Description SITCDR transmit data is valid TCD is cleared to 0 in the following cases: •...
Page 673 Section 15 Serial I/O with FIFO (SIOF) Bit 2—Receive Overrun Error (RERR): Flag that indicates the occurrence of a receive overrun. Bit 2: RERR Description Reception is in progress, or has ended normally (Initial value) [Clearing conditions] • When 0 is written to the RERR bit after reading RERR = 1 •...
Page 674: Receive Control Data Register (Sircdr)
Section 15 Serial I/O with FIFO (SIOF) Bit 0—Receive Data Register Full (RDRF): Flag that indicates that SIRDR receive data is waiting. Bit 0: RDRF Description Indicates that the amount of primary receive data in SIRDR is less than the receive FIFO watermark setting (Initial value) RDRF is cleared to 0 in the following cases:...
Page 675: Transmit Control Data Register (Sitcdr)
Section 15 Serial I/O with FIFO (SIOF) 15.2.8 Transmit Control Data Register (SITCDR) Bit: Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W SITCDR is a register that stores transmit control data. Data should be written to SITCDR when the TCD bit is set to 1 in SISTR (SITCDR transmit data invalid).
Page 676 Section 15 Serial I/O with FIFO (SIOF) It also contains a bit used to select LSB first or MSB first when transmitting and receiving to match the connected codec, as well as a bit for controlling the LSB for transmitted primary data and control data.
Page 677 Section 15 Serial I/O with FIFO (SIOF) Bit 8—Transmit FIFO Data Register Reset (TFRST): Invalidates the transmit data in SITDR and resets it to empty status. Also initializes the TERR and TDRE bits in SISTR. Note that SICTR is not initialized, so transmitting continues if the TE bit is set to 1. Bit 8: TFRST Description Reset disabled...
Page 678 Section 15 Serial I/O with FIFO (SIOF) Bit 3 to 0— Transmit FIFO Watermark (TFWM3 to TFWM0): These bits are used to make threshold settings, which are used to set the TDRE bit in SISTR. When the amount of primary send data in SITDR is less than or equal to the watermark setting, as shown in the table below, the TDRE bit is set to 1.
Page 679: Fifo Data Count Register (Sifdr)
Section 15 Serial I/O with FIFO (SIOF) 15.2.10 FIFO Data Count Register (SIFDR) Bit:       R4 R3 R2 R1 R0 T4 T3 T2 T1 T0 Initial value: R/W: SIFDR is a register that indicates the amount of primary data stored in SIRDR and SITDR. The upper 8 bits indicate the amount of primary receive data stored in SIRDR, and the lower 8 bits indicate the amount of primary transmit data stored in SITDR.
Page 680: Operation
Section 15 Serial I/O with FIFO (SIOF) 15.3 Operation 15.3.1 Input when TRMD = 0 in SIFCR Figure 15.2 shows interval transfer mode (SE set to 1 in SICTR) with MSB first (LM cleared to 0 in SIFCR). Figure 15.3 shows continuous transfer mode (SE cleared to 0 in SICTR) with MSB first (LM cleared to 0 in SIFCR).
Page 681 Section 15 Serial I/O with FIFO (SIOF) Set to 1 when an amount of data equal to or greater than the setting of bits RFWM3 to RFWM0 in SIFCR is received RDRF Synchronous internal clock SIRDR A[7:0] SIRSR A[7] A[7:6] A[7:1] A[7:0] B[7]...
Page 682 Section 15 Serial I/O with FIFO (SIOF) Figure 15.4 shows interval transfer mode (SE set to 1 in SICTR) with LSB first (LM set to 1 in SIFCR). Figure 15.5 shows continuous transfer mode (SE cleared to 0 in SICTR) with LSB first (LM set to 1 in SIFCR).
Page 683: Output When Trmd = 0 In Sifcr
Section 15 Serial I/O with FIFO (SIOF) 15.3.2 Output when TRMD = 0 in SIFCR Figure 15.6 shows interval transfer mode when TM is cleared to 0 in SICTR and with MSB first. Figure 15.7 shows continuous transfer mode when TM is cleared to 0 in SICTR and with MSB first.
Page 684 Section 15 Serial I/O with FIFO (SIOF) Set to 1 when the amount of data in SITDR is Cleared to 0 when an amount of data exceeding the setting of bits TFWM3 to TFWM0 in SIFCR less than or equal to the setting of bits has been written to SITDR TFWM3 to TFWM0 in SIFCR TDRE...
Page 685 Section 15 Serial I/O with FIFO (SIOF) Set to 1 when the amount of data in SITDR is Cleared to 0 when an amount of data exceeding the setting of bits TFWM3 to TFWM0 in SIFCR less than or equal to the setting of bits has been written to SITDR TFWM3 to TFWM0 in SIFCR TDRE...
Page 686 Section 15 Serial I/O with FIFO (SIOF) Set to 1 when the amount of data in SITDR is Cleared to 0 when an amount of data exceeding the setting of bits TFWM3 to TFWM0 in SIFCR less than or equal to the setting of bits has been written to SITDR TFWM3 to TFWM0 in SIFCR TDRE...
Page 687: Output When Trmd = 1 In Sifcr
Section 15 Serial I/O with FIFO (SIOF) Set to 1 when the amount of data in SITDR is Cleared to 0 when an amount of data exceeding the setting of bits TFWM3 to TFWM0 in SIFCR less than or equal to the setting of bits has been written to SITDR TFWM3 to TFWM0 in SIFCR TDRE...
Page 688 Section 15 Serial I/O with FIFO (SIOF) Figure 15.14 Transmission: TRMD = 1 Mode Rev. 2.00 Mar 09, 2006 page 662 of 906 REJ09B0292-0200...
Page 689: Siof Interrupt Sources And Dmac
Section 15 Serial I/O with FIFO (SIOF) 15.4 SIOF Interrupt Sources and DMAC Each SIOF channel has four interrupt sources: the receive-overrun-error interrupt (RERI0) request, transmit-underrun-error interrupt (TERI0) request, receive-data-full interrupt/receive-control-data- register-full interrupt (RDFI0) request, and transmit-data-empty interrupt/transmit-control-data- register-empty interrupt (TDEI0) request. Table 15.3 shows the interrupt sources and their relative priorities.
Page 690 Section 15 Serial I/O with FIFO (SIOF) Channel interrupt priority levels are set by means of the IRPE register, as described in section 5, Interrupt Controller (INTC). Table 15.3 SIOF Interrupt Sources Interrupt Source Description DMAC Activation Priority RERI0 Receive overrun error (RERR) Not possible High ↑...
Page 691: Section 16 Serial I/O (Sio)
Section 16 Serial I/O (SIO) Section 16 Serial I/O (SIO) 16.1 Overview A two-channel simple synchronous serial I/O is provided on-chip. The serial I/O functions mainly as an interface between the chip and a codec or modem analog front-end. 16.1.1 Features The serial I/O has the following features: •...
Page 692 Section 16 Serial I/O (SIO) Peripheral bus SISTR SITDR SIRDR SICTR Bit counter I/O control unit SITSR SIRSR Serial I/O module (SIO) SRxD SRCK SRS STS STCK STxD SIRDR: Receive data register SIRSR: Receive shift register SISTR: Serial status register SICTR: Serial control register SITDR: Transmit data register SITSR: Transmit shift register...
Page 693 Section 16 Serial I/O (SIO) Table 16.1 shows the functions of the external pins. As the channels are independent, the channel numbers are omitted from the signal names in the rest of this section. Table 16.1 Serial I/O (SIO) External Pins Channel Name Function...
Page 694: Register Configuration
Section 16 Serial I/O (SIO) 16.2 Register Configuration Table 16.2 shows the SIO’s registers. As the channels are independent, the channel numbers are omitted from the signal names in the rest of this section. Table 16.2 Register Configuration Abbrevia- Initial Access Size Channel Register tion...
Page 695: Receive Shift Register (Sirsr)
Section 16 Serial I/O (SIO) 16.2.1 Receive Shift Register (SIRSR) Bit: Initial value: — — — — — — — R/W: — — — — — — — SIRSR is a 16-bit register used to receive serial data. The data is fetched in MSB first from the SRxD pin in synchronization with the fall of the serial receive clock (SRCK), and is shifted into SIRSR.
Page 696: Transmit Shift Register (Sitsr)
Section 16 Serial I/O (SIO) 16.2.3 Transmit Shift Register (SITSR) Bit: Initial value: — — — — — — — R/W: — — — — — — — SITSR is a 16-bit register used to transmit serial data. The contents of this register are shifted in MSB-first order in synchronization with the rising edge of the serial transmit clock (STCK), and output from the STxD pin.
Page 697: Serial Control Register (Sictr)
Section 16 Serial I/O (SIO) 16.2.5 Serial Control Register (SICTR) Bit: — — — — — — — — Initial value: R/W: Bit: — Initial value: R/W: SICTR is a 16-bit register used to set parameters for serial port control. SICTR is initialized to H'0000 by a reset.
Page 698 Section 16 Serial I/O (SIO) Bit 4—Transmit/Receive Data Length Select (DL): Specifies the serial I/O module’s transfer data length. The initial value of this bit is 0, indicating an 8-bit data length. When an 8-bit data length is specified, the lower 8 bits of each I/O register are used. Bit 4: DL Description 8-bit transfer data length...
Page 699: Serial Status Register (Sistr)
Section 16 Serial I/O (SIO) 16.2.6 Serial Status Register (SISTR) Bit: — — — TERR RERR TDRE RDRF Initial value: R/W: R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 should be written, to clear the flag. SISTR is a 16-bit register that indicates the status of the serial I/O module. SISTR is initialized to H'0002 by a reset.
Page 700 Section 16 Serial I/O (SIO) Bit 1—Transmit Data Register Empty (TDRE): Flag that indicates that the SITDR register is empty and the next data can be written. Bit 1: TDRE Description SITDR transmit data is valid [Clearing conditions] • When 0 is written to the TDRE bit after reading TDRE = 1 •...
Page 701: Operation
Section 16 Serial I/O (SIO) 16.3 Operation 16.3.1 Input Figure 16.2 shows interval transfer mode (SE set to 1 in SICTR), and figure 16.3 shows continuous transfer mode (SE cleared to 0 in SICTR). RDRF synchronous internal clock SIRDR A[7:0] SIRSR Undefined A[7]...
Page 702: Output
Section 16 Serial I/O (SIO) 16.3.2 Output Figure 16.4 shows interval transfer mode (SE set to 1 in SICTR) when TM is cleared to 0 in SICTR. Figure 16.5 shows continuous transfer mode (SE cleared to 0 in SICTR) when TM is cleared to 0 in SICTR.
Page 703 Section 16 Serial I/O (SIO) TDRE synchronous internal clock SITDR Data C SITSR C[7:0] C[6:0] C[5:0] C[0] D[7:0] D[6:0] D[5:0] D[4:0] Undefined STCK C[7] C[6] C[5] C[1] C[0] D[7] D[6] D[5] STxD Notes: TM = 0: STS is input DL = 0: 8-bit data transfer SE = 0: Asynchronous transfer, no start signal mode Figure 16.5 Transmission: Continuous Transfer Mode (TM = 0 Mode) TDRE...
Page 704 Section 16 Serial I/O (SIO) TDRE synchronous internal clock SITDR Data C SITSR Undefined C[7:0] C[6:0] C[5:0] C[0] D[7:0] D[6:0] D[5:0] D[4:0] STCK STxD C[7] C[6] C[5] C[1] C[0] D[7] D[6] D[5] Notes: TM = 1: STS is output DL = 0: 8-bit data transfer SE = 0: Asynchronous transfer, no start signal mode Figure 16.7 Transmission: Continuous Transfer Mode (TM = 1 Mode) Rev.
Page 705: Sio Interrupt Sources And Dmac
Section 16 Serial I/O (SIO) 16.4 SIO Interrupt Sources and DMAC Each SIO channel has four interrupt sources: the receive-overrun-error interrupt (RERI) request, transmit-underrun-error interrupt (TERI) request, receive-data-full interrupt (RDFI) request, and transmit-data-empty interrupt (TDEI) request. Table 16.3 shows the interrupt sources and their relative priorities.
Page 706 Section 16 Serial I/O (SIO) Rev. 2.00 Mar 09, 2006 page 680 of 906 REJ09B0292-0200...
Page 707: Section 17 16-Bit Timer Pulse Unit (Tpu)
Section 17 16-Bit Timer Pulse Unit (TPU) Section 17 16-Bit Timer Pulse Unit (TPU) 17.1 Overview An on-chip 16-bit timer pulse unit (TPU) is provided that comprises three 16-bit timer channels. 17.1.1 Features The TPU has the following features: • Maximum 8-pulse input/output •...
Page 708 Section 17 16-Bit Timer Pulse Unit (TPU)  For channels 1, and 2, two compare match/input capture dual-function interrupts, one overflow interrupt, and one underflow interrupt can be requested independently • Automatic transfer of register data  Block transfer, 1-word data transfer, and 1-byte data transfer possible by direct memory access controller (DMAC) activation Table 17.1 lists the functions of the TPU.
Page 709 Section 17 16-Bit Timer Pulse Unit (TPU) Item Channel 0 Channel 1 Channel 2 DMAC activation TGR compare match or — — input capture Interrupt sources 5 sources 4 sources 4 sources • • • Compare match or Compare match or Compare match or input capture 0A input capture 1A...
Page 710: Block Diagram
Section 17 16-Bit Timer Pulse Unit (TPU) 17.1.2 Block Diagram Figure 17.1 shows a block diagram of the TPU. Clock input Internal clock: Pφ/1 Pφ/4 Pφ/16 Pφ/64 Internal data bus Pφ/256 Pφ/1024 External clock: TCLKA TCLKB TCLKC TCLKD Interrupt request signals I/O pins Channel 0: TGI0A...
Page 711: Pin Configuration
Section 17 16-Bit Timer Pulse Unit (TPU) 17.1.3 Pin Configuration Table 17.2 shows the pin configuration of the TPU. Table 17.2 Pin Configuration Channel Name Abbreviation Function Clock input A TCLKA Input External clock A input pin (Channel 1 phase counting mode A phase input) Clock input B TCLKB...
Page 712: Register Configuration
Section 17 16-Bit Timer Pulse Unit (TPU) 17.1.4 Register Configuration Table 17.3 shows the register configuration of the TPU. Table 17.3 Register Configuration Initial Access Channel Name Abbreviation R/W Value Address size (Bits) Timer control register 0 TCR0 H'00 H'FFFFFC50 8,16 Timer mode register 0 TMDR0 H'C0...
Page 713: Register Descriptions
Section 17 16-Bit Timer Pulse Unit (TPU) Initial Access Channel Name Abbreviation R/W Value Address size (Bits) Timer control register 2 TCR2 H'00 H'FFFFFC70 8, 16 Timer mode register 2 TMDR2 H'C0 H'FFFFFC71 8, 16 Timer I/O control TIOR2 H'00 H'FFFFFC72 8, 16 register 2...
Page 714 Section 17 16-Bit Timer Pulse Unit (TPU) The TCR registers are 8-bit registers that control the TCNT channels. The TPU has three TCR registers, one for each of channels 0 to 2. The TCR registers are initialized to H'00 by a reset. TCNT operation should be stopped when making TCR settings.
Page 715 Section 17 16-Bit Timer Pulse Unit (TPU) Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge. When a both-edges count is selected, a clock divided by two from the input clock can be selected. (e.g.
Page 716: Timer Mode Register (Tmdr)
Section 17 16-Bit Timer Pulse Unit (TPU) Bit 2: Bit 1: Bit 0: Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on Pφ/1 (Initial value) Internal clock: counts on Pφ/4 Internal clock: counts on Pφ/16 Internal clock: counts on Pφ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on Pφ/256...
Page 717 Section 17 16-Bit Timer Pulse Unit (TPU) The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode for each channel. The TPU has three TMDR registers, one for each channel. The TMDR registers are initialized to H'C0 by a reset. TCNT operation should be stopped when making TMDR settings.
Page 718: Timer I/O Control Register (Tior)
Section 17 16-Bit Timer Pulse Unit (TPU) Bits 3 to 0—Modes 3 to 0 (MD3 to MD0): These bits are used to set the timer operating mode. Bit 3: Bit 2: Bit 1: Bit 0: MD3 * MD2 * Description Normal operation (Initial value) Reserved...
Page 719 Section 17 16-Bit Timer Pulse Unit (TPU) The TIOR registers are 8-bit registers that control the TGR registers. The TPU has four TIOR registers, two for channel 0 and one each for channels 1, and 2. The TIOR registers are initialized to H'00 by a reset.
Page 720 Section 17 16-Bit Timer Pulse Unit (TPU) TIOR0L Bit 7: Bit 6: Bit 5: Bit 4: Channel IOD3 IOD2 IOD1 IOD0 Description TGR0D Output disabled (Initial value) isoutput Initial output is 0 0 output at compare match compare output 1 output at compare match register * Toggle output at compare match...
Page 721 Section 17 16-Bit Timer Pulse Unit (TPU) TIOR1 Bit 7: Bit 6: Bit 5: Bit 4: Channel IOB3 IOB2 IOB1 IOB0 Description TGR1B is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare...
Page 722 Section 17 16-Bit Timer Pulse Unit (TPU) Bits 3 to 0— I/O Control A3 to A0 (IOA3 to IOA0) I/O Control C3 to C0 (IOC3 to IOC0): IOA3 to IOA0 specify the function of TGRA. IOC3 to IOC0 specify the function of TGRC. TIOR0H Bit 3: Bit 2:...
Page 723 Section 17 16-Bit Timer Pulse Unit (TPU) TIOR0L Bit 3: Bit 2: Bit 1: Bit 0: Channel IOC3 IOC2 IOC1 IOC0 Description TGR0C is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register * Toggle output at compare...
Page 724 Section 17 16-Bit Timer Pulse Unit (TPU) TIOR1 Bit 3: Bit 2: Bit 1: Bit 0: Channel IOA3 IOA2 IOA1 IOA0 Description TGR1A is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare...
Page 725: Timer Interrupt Enable Register (Tier)
Section 17 16-Bit Timer Pulse Unit (TPU) 17.2.4 Timer Interrupt Enable Register (TIER) Channel 0: TIER0 Bit: — — — TCIEV TGIED TGIEC TGIEB TGIEA Initial value: R/W: Channel 1: TIER1 Channel 2: TIER2 Bit: — — TCIEU TCIEV — —...
Page 726 Section 17 16-Bit Timer Pulse Unit (TPU) Bit 3—TGR Interrupt Enable D (TGIED): Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channel 0. In channels 1, and 2, bit 3 is reserved. It is always read as 0 and cannot be modified. Bit 3: TGIED Description Interrupt requests (TGID) by TGFD bit disabled...
Page 727: Timer Status Register (Tsr)
Section 17 16-Bit Timer Pulse Unit (TPU) 17.2.5 Timer Status Register (TSR) Channel 0: TSR0 Bit: — — — TCFV TGFD TGFC TGFB TGFA Initial value: R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/W: Note: * Only 0 can be written, to clear the flags. Channel 1: TSR1 Channel 2: TSR2 Bit:...
Page 728 Section 17 16-Bit Timer Pulse Unit (TPU) Bit 5—Underflow Flag (TCFU): Status flag that indicates that TCNT underflow has occurred when channels 1 and 2 are set to phase counting mode. In channel 0, bit 5 is reserved. It is always read as 0 and cannot be modified. Bit 5: TCFU Description [Clearing condition]...
Page 729 Section 17 16-Bit Timer Pulse Unit (TPU) Bit 2—Input Capture/Output Compare Flag C (TGFC): Status flag that indicates the occurrence of TGRC input capture or compare match in channel 0. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and cannot be modified. Bit 2: TGFC Description [Clearing conditions]...
Page 730: Timer Counter (Tcnt)
Section 17 16-Bit Timer Pulse Unit (TPU) Bit 0—Input Capture/Output Compare Flag A (TGFA): Status flag that indicates the occurrence of TGRA input capture or compare match. Bit 0: TGFA Description [Clearing conditions] (Initial value) • When DMAC is activated by TGIA interrupt while DRCR setting in DMAC is TGI0A •...
Page 731: Timer General Register (Tgr)
Section 17 16-Bit Timer Pulse Unit (TPU) 17.2.7 Timer General Register (TGR) Bit: Initial value: R/W: Bit: Initial value: R/W: The TGR registers are 16-bit registers with a dual function as output compare and input capture registers. The TPU has 8 TGR registers, four for channel 0 and two each for channels 1, and 2. TGRC and TGRD for channel 0 can also be designated for operation as buffer registers*.
Page 732: Timer Synchronous Register (Tsyr)
Section 17 16-Bit Timer Pulse Unit (TPU) Bits 2 to 0—Counter Start 2 to 0 (CST2 to CST0): These bits select operation or stoppage for TCNT. Bit n: CSTn Description TCNTn count operation is stopped (Initial value) TCNTn performs count operation Note: n = 2 to 0 If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops, but the TIOC pin output compare output level is retained.
Page 733: Interface To Bus Master
Section 17 16-Bit Timer Pulse Unit (TPU) 17.3 Interface to Bus Master 17.3.1 16-Bit Registers TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. These registers cannot be read or written to in 8-bit units;...
Page 734 Section 17 16-Bit Timer Pulse Unit (TPU) Examples of 8-bit register access operation are shown in figures 17.3, 17.4, and 17.5. Internal data bus Module Bus interface master data bus Figure 17.3 8-Bit Register Access Operation [Bus Master ↔ ↔ ↔ ↔...
Page 735: Operation
Section 17 16-Bit Timer Pulse Unit (TPU) 17.4 Operation 17.4.1 Overview Operation in each mode is outlined below. Normal Operation: Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register.
Page 736: Basic Functions
Section 17 16-Bit Timer Pulse Unit (TPU) 17.4.2 Basic Functions Counter Operation: When one of bits CST0 to CST2 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on.
Page 737 Section 17 16-Bit Timer Pulse Unit (TPU) • Free-running count operation and periodic count operation Immediately after a reset, the TPU’s TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up- count operation as a free-running counter.
Page 738 Section 17 16-Bit Timer Pulse Unit (TPU) Figure 17.8 illustrates periodic counter operation. Counter cleared by TGR TCNT value compare match H'0000 Time CST bit Flag cleared by software or DMAC activation Figure 17.8 Periodic Counter Operation Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match.
Page 739 Section 17 16-Bit Timer Pulse Unit (TPU) • Examples of waveform output operation Figure 17.10 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change.
Page 740 Section 17 16-Bit Timer Pulse Unit (TPU) Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. •...
Page 741 Section 17 16-Bit Timer Pulse Unit (TPU) • Example of input capture operation Figure 17.13 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
Page 742: Synchronous Operation
Section 17 16-Bit Timer Pulse Unit (TPU) 17.4.3 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base.
Page 743 Section 17 16-Bit Timer Pulse Unit (TPU) Example of Synchronous Operation: Figure 17.15 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGR0B compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source.
Page 744: Buffer Operation
Section 17 16-Bit Timer Pulse Unit (TPU) 17.4.4 Buffer Operation Buffer operation, provided for channel 0 enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register.
Page 745 Section 17 16-Bit Timer Pulse Unit (TPU) • When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 17.17.
Page 746 Section 17 16-Bit Timer Pulse Unit (TPU) Examples of Buffer Operation • When TGR is an output compare register Figure 17.19 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B.
Page 747: Pwm Modes
Section 17 16-Bit Timer Pulse Unit (TPU) • When TGR is an input capture register Figure 17.20 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge.
Page 748 Section 17 16-Bit Timer Pulse Unit (TPU) • PWM mode 1 PWM output is generated by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA3–IOA0 and IOC3–IOC0 in TIOR is performed in response to compare match A and C, and the output specified by bits IOB3–IOB0 and IOD3–IOD0 in TIOR in response to compare match B and D, from pins TIOCA and TIOCC.
Page 749 Section 17 16-Bit Timer Pulse Unit (TPU) Example of PWM Mode Setting Procedure: Figure 17.21 shows an example of the PWM mode setting procedure. Select the counter clock with bits TPSC2 to PWM mode TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR.
Page 750 Section 17 16-Bit Timer Pulse Unit (TPU) TCNT value Counter cleared by TGRA compare match TGRA TGRB H'0000 Time TIOCA Figure 17.22 Example of PWM Mode Operation (1) Figure 17.23 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGR1B compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers, to output a 5-phase PWM waveform.
Page 751 Section 17 16-Bit Timer Pulse Unit (TPU) Figure 17.24 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode. TCNT value TGRB rewritten TGRA TGRB TGRB rewritten TGRB rewritten H'0000 Time 0% duty TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten...
Page 752: Phase Counting Mode
Section 17 16-Bit Timer Pulse Unit (TPU) 17.4.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR.
Page 753 Section 17 16-Bit Timer Pulse Unit (TPU) Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. •...
Page 754 Section 17 16-Bit Timer Pulse Unit (TPU) • Phase counting mode 2 Figure 17.27 shows an example of phase counting mode 2 operation, and table 17.9 summarizes the TCNT up/down-count conditions. TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) TCNT value Up-count...
Page 755 Section 17 16-Bit Timer Pulse Unit (TPU) • Phase counting mode 3 Figure 17.28 shows an example of phase counting mode 3 operation, and table 17.10 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count...
Page 756 Section 17 16-Bit Timer Pulse Unit (TPU) • Phase counting mode 4 Figure 17.29 shows an example of phase counting mode 4 operation, and table 17.11 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count...
Page 757: Interrupts
Section 17 16-Bit Timer Pulse Unit (TPU) 17.5 Interrupts 17.5.1 Interrupt Sources and Priorities There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing generation of interrupt request signals to be enabled or disabled individually.
Page 758: Dmac Activation
Section 17 16-Bit Timer Pulse Unit (TPU) Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel.
Page 759: Operation Timing
Section 17 16-Bit Timer Pulse Unit (TPU) 17.6 Operation Timing 17.6.1 Input/Output Timing TCNT Count Timing: Figure 17.30 shows TCNT count timing in internal clock operation, and figure 17.31 shows TCNT count timing in external clock operation. Pφ Falling edge Rising edge Internal clock TCNT...
Page 760 Section 17 16-Bit Timer Pulse Unit (TPU) Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin).
Page 761 Section 17 16-Bit Timer Pulse Unit (TPU) Timing for Counter Clearing by Compare Match/Input Capture: Figure 17.34 shows the timing when counter clearing by compare match occurrence is specified, and figure 17.35 shows the timing when counter clearing by input capture occurrence is specified. Pφ...
Page 762 Section 17 16-Bit Timer Pulse Unit (TPU) Buffer Operation Timing: Figures 17.36 and 17.37 show the timing in buffer operation. Pφ TCNT Compare match signal TGRA, TGRB TGRC, TGRD Figure 17.36 Buffer Operation Timing (Compare Match) Pφ Input capture signal TCNT TGRA, TGRB...
Page 763: Interrupt Signal Timing
Section 17 16-Bit Timer Pulse Unit (TPU) 17.6.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 17.38 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal timing.
Page 764 Section 17 16-Bit Timer Pulse Unit (TPU) TGF Flag Setting Timing in Case of Input Capture: Figure 17.39 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and TGI interrupt request signal timing. Pφ Input capture signal TCNT...
Page 765 Section 17 16-Bit Timer Pulse Unit (TPU) Pφ TCNT input clock TCNT H'0000 H'FFFF (underflow) Underflow signal TCFU flag TCIU interrupt Figure 17.41 TCIU Interrupt Setting Timing Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it.
Page 766: Usage Notes
Section 17 16-Bit Timer Pulse Unit (TPU) DMAC DMAC read cycle write cycle Pφ Destination Source address Address address Status flag Interrupt request signal Figure 17.43 Timing for Status Flag Clearing by DMAC Activation 17.7 Usage Notes Note that the kinds of operation and contention described below occur during TPU operation. Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection.
Page 767 Section 17 16-Bit Timer Pulse Unit (TPU) Caution on Period Setting: When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated).
Page 768 Section 17 16-Bit Timer Pulse Unit (TPU) Contention between TCNT Write and Increment Operations: If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 17.46 shows the timing in this case. TCNT write cycle Pφ...
Page 769 Section 17 16-Bit Timer Pulse Unit (TPU) Contention between TGR Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the same value as before is written. Figure 17.47 shows the timing in this case.
Page 770 Section 17 16-Bit Timer Pulse Unit (TPU) Contention between Buffer Register Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the write data.
Page 771 Section 17 16-Bit Timer Pulse Unit (TPU) Contention between TGR Read and Input Capture: If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data before input capture transfer. Figure 17.49 shows the timing in this case.
Page 772 Section 17 16-Bit Timer Pulse Unit (TPU) Contention between TGR Write and Input Capture: If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed.
Page 773 Section 17 16-Bit Timer Pulse Unit (TPU) Contention between Buffer Register Write and Input Capture: If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 17.51 shows the timing in this case.
Page 774 Section 17 16-Bit Timer Pulse Unit (TPU) Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 17.52 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR.
Page 775 Section 17 16-Bit Timer Pulse Unit (TPU) Contention between TCNT Write and Overflow/Underflow: If there is an up-count or down- count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set . Figure 17.53 shows the operation timing in the case of contention between a TCNT write and overflow.
Page 776: Usage Notes
Section 17 16-Bit Timer Pulse Unit (TPU) 17.8 Usage Notes 17.8.1 Clearing Flags in TSR0 to TSR2 When bits TCFV, TGFD, TGFC, TGFB, and TGFA in TSR0, and bits TCFU, TCFV, TGFB, and TGFA in TSR1 and TSR2, are cleared, it may happen that the interrupt request in the internal logic cannot be cleared although the flag is cleared.
Page 777: Section 18 User Debug Interface (H-Udi)
Section 18 User Debug Interface (H-UDI) Section 18 User Debug Interface (H-UDI) 18.1 Overview The user debug interface (H-UDI) provides data transfer and interrupt request functions. The H- UDI performs serial transfer by means of external signal control. 18.1.1 Features The H-UDI has the following features conforming to the IEEE 1149.1 standard.
Page 778: H-Udi Block Diagram
Section 18 User Debug Interface (H-UDI) 18.1.2 H-UDI Block Diagram Figure 18.1 shows a block diagram of the H-UDI. Internal H-UDI controller bus controller interrupt signal TRST Decoder SDIR SDSR SDDRH SDDRL SDIDR SDIR: Instruction register TCK: Test clock SDSR: Status register TMS: Test mode select...
Page 779: Pin Configuration
Section 18 User Debug Interface (H-UDI) 18.1.3 Pin Configuration Table 18.1 shows the H-UDI pin configuration. Table 18.1 Pin Configuration Pin Name Abbreviation Function Test clock Input Test clock input Test mode select Input Test mode select input signal Test data input Input Serial data input Test data output...
Page 780: External Signals
Section 18 User Debug Interface (H-UDI) TDO in the IDCODE mode. All registers, except SDBPR, SDBSR, and SDIDR, can be accessed from the CPU. Table 18.3 shows the kinds of serial transfer possible with each register. Table 18.3 H-UDI Register Serial Transfer Register Serial Input Serial Output...
Page 781: Test Data Output (Tdo)
Section 18 User Debug Interface (H-UDI) 18.2.4 Test Data Output (TDO) The test data output pin (TDO) performs serial output of instructions and data from H-UDI registers. Transfer is performed in synchronization with TCK. If there is no output, TDO goes to the high-impedance state.
Page 782 Section 18 User Debug Interface (H-UDI) Table 18.4 Instruction Configuration Bit 15: Bit 14: Bit 13: Bit 12: Description EXTEST mode Reserved CLAMP mode HIGHZ mode SAMPLE/PRELOAD mode Reserved Reserved Reserved Reserved Reserved H-UDI interrupt Reserved Reserved Reserved IDCODE mode (Initial value) BYPASS mode Bits 11 to 0—Reserved: These bits are always read as 0.
Page 783: Status Register (Sdsr)
Section 18 User Debug Interface (H-UDI) 18.3.2 Status Register (SDSR) Bit: — — — — — — — — Initial value: R/W: Bit: — — — — — — — SDTRF Initial value: R/W: The status register (SDSR) is a 16-bit register that can be read and written to by the CPU. Output from TDO is possible for SDSR, but serial data cannot be written to SDSR via TDI.
Page 784: Data Register (Sddr)
Section 18 User Debug Interface (H-UDI) 18.3.3 Data Register (SDDR) The data register (SDDR) comprises data register H (SDDRH) and data register L (SDDRL), each of which has the following configuration. Bit: Initial value: — — — — — — —...
Page 785 Section 18 User Debug Interface (H-UDI) Table 18.5 shows the relationship between the terminals of the LSI and the boundary scan register. Table 18.5 Correspondence between Pins and Boundary Scan Register Bits Pin No. Pin Name Input/Output Bit No. from TDI Input Output Output enable...
Page 786 Section 18 User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. Input Output Output enable Input Output Output enable Input Output Output enable Input Output Output enable Input Output Output enable Input Output Output enable Input Output Output enable Input Output Output enable...
Page 787 Section 18 User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. Input Output Output enable Input Output Output enable Input Output Output enable Input Output Output enable Input Output Output enable Input Output Output enable Input Output Output enable Input Output Output enable...
Page 788 Section 18 User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. Input Output Output enable Input Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable...
Page 789 Section 18 User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output...
Page 790 Section 18 User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. DQMUU/WE3 Output Output enable DQMUL/WE2 Output Output enable DQMLU/WE1 Output Output enable DQMLL/WE0 Output Output enable CAS3 Output Output enable CAS2 Output Output enable CAS1 Output Output enable CAS0 Output Output enable...
Page 791 Section 18 User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. Output Output enable Output Output enable Output Output enable BUSHIZ Input Output Output enable DREQ1 Input DREQ0 Input DACK1 Output Output enable DACK0 Output Output enable BRLS Input Output Output enable...
Page 792 Section 18 User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. PB11 Input Output Output enable PB10 Input Output Output enable Input Output Output enable Input Output Output enable Input Output Output enable Input Output Output enable Input Output Output enable Input...
Page 793 Section 18 User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. Input Output Output enable Input Output Output enable PA13 Input Output Output enable PA12 Input Output Output enable PA11 Input Output Output enable PA10 Input Output Output enable Input Output Output enable...
Page 794 Section 18 User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. Input Output Output enable Input Output Output enable CKPO Output Output enable Input Output Output enable Input Output Output enable Input Output Output enable RX–ER Input RX–DV Input Input Input...
Page 795 Section 18 User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. TX–CLK Input TX–EN Output Output enable ETXD0 Output Output enable ETXD1 Output Output enable ETXD2 Output Output enable ETXD3 Output Output enable TX–ER Output Output enable IRL3 Input IRL2 Input...
Page 796: Id Code Register (Sdidr)
Section 18 User Debug Interface (H-UDI) 18.3.6 ID code register (SDIDR) The ID code register (SDIDR) is a 32-bit register. In the IDCODE mode, SDIDR can output H'0005200F, which is a fixed code, from TDO. However, no serial data can be written to SDIDR via TDI.
Page 797: Operation
Section 18 User Debug Interface (H-UDI) 18.4 Operation 18.4.1 TAP Controller Figure 18.2 shows the internal states of TAP controller. State transitions basically conform with the JTAG standard. Test-logic-reset Run-test/idle Select-DR-scan Select-IR-scan Capture-DR Capture-IR Shift-DR Shift-IR Exit1-DR Exit1-IR Pause-DR Pause-IR Exit2-DR Exit2-IR Update-DR...
Page 798: H-Udi Interrupt And Serial Transfer
Section 18 User Debug Interface (H-UDI) 18.4.2 H-UDI Interrupt and Serial Transfer When an H-UDI interrupt instruction is transferred to SDIR via TDI, an interrupt is generated. Data transfer can be controlled by means of the H-UDI interrupt service routine. Transfer can be performed by means of SDDR.
Page 799 Section 18 User Debug Interface (H-UDI) Input/ Instruction output SDTRF Input Serial data H-UDI interrupt request Shift disabled SDTRF Shift Shift enabled enabled (in SDSR) SDSR and SDDR SDDR SDSR SDSR SDDR MUX SDDR access Shift Shift state SDSR serial transfer (monitoring) Notes: 1.
Page 800 Section 18 User Debug Interface (H-UDI) TRST SDTRF Figure 18.4 Data Input/Output Timing Chart (2) TRST SDTRF SDTRF Figure 18.5 Data Input/Output Timing Chart (3) Rev. 2.00 Mar 09, 2006 page 774 of 906 REJ09B0292-0200...
Page 801: H-Udi Reset
When this instruction is executing, the SH7616’s input pin signals are transmitted directly to the internal circuitry, and internal circuit values are directly output externally from the output pins.
Page 802 Section 18 User Debug Interface (H-UDI) EXTEST: This instruction is provided to test external circuitry when the SH7616 is mounted on a printed circuit board. When this instruction is executed, output pins are used to output test data (previously set by the SAMPLE/PRELOAD instruction) from the boundary scan register to the printed circuit board, and input pins are used to latch test results into the boundary scan register from the printed circuit board.
Page 803: Notes On Use
Section 18 User Debug Interface (H-UDI) 18.5.2 Notes on Use 1. Boundary scan mode does not cover clock-related signals (EXTAL, XTAL, CKIO, CAP1, CAP2). 2. Boundary scan mode does not cover reset-related signals (RES, ASEMODE). 3. Boundary scan mode does not cover H-UDI-related signals (TCK, TDI, TDO, TMS, TRST). Fix the ASEMODE pin high.
Page 804 Section 18 User Debug Interface (H-UDI) • SDIR and SDSR serial data input/output In Capture-IR, SDIR and SDSR are captured into the shift register, and in Shift-IR bits 0 to 15 of SDSR and bits 0 to 15 of SDIR are output in that order from TDO. In Update-IR, data input from TDI is written to SDIR, but not to SDSR.
Page 805 Section 18 User Debug Interface (H-UDI) • SDDRH and SDDRL serial data input/output (1) In H-UDI interrupt mode, before SDTRF = 1 is read from TDO when an H-UDI interrupt is generated, SDSR and SDIR are captured into the shift register in Capture-DR, and in Shift-DR bits 0 to 15 of SDSR and bits 0 to 15 of SDIR are output in that order from TDO.
Page 806 Section 18 User Debug Interface (H-UDI) • SDIDR serial data input/output In IDCODE mode, SDIDR is captured into the shift register in Capture-DR, and in Shift-DR bits 0 to 31 of SDIDR are output in that order from TDO. In Update-DR, data input from TDI is not written to any register. Bit 31 Bit 15 Shift register...
Page 807: Section 19 Pin Function Controller (Pfc)
Section 19 Pin Function Controller (PFC) Section 19 Pin Function Controller (PFC) 19.1 Overview The pin function controller (PFC) consists of registers to select multiplexed pin functions and input/output direction. The pin function and input/output direction can be selected for individual pins regardless of the operating mode of the chip.
Page 808 Section 19 Pin Function Controller (PFC) Table 19.1 Multiplex Pins Function 1 [00]* Function 2 [01]* Function 3 [10]* Function 4 [11]* Signal Related Signal Related Signal Related Signal Related Port Name Module Name Module Name Module Name Module PA13 Port SRCK0 SIO0...
Page 809: Register Configuration
Section 19 Pin Function Controller (PFC) 19.2 Register Configuration Table 19.2 shows the PFC registers. Table 19.2 Register Configuration Name Abbreviation Initial Value Address Access Size Port A control register PACR H'0000 H'FFFFFC80 8, 16 Port A I/O register PAIOR H'0000 H'FFFFFC82 8, 16...
Page 810 Section 19 Pin Function Controller (PFC) Bit 13—PA13 Mode Bit (PA13MD): Selects the function of pin PA13/SRCK0. Bit 13: PA13MD Description General input/output (PA13) (Initial value) SIOF serial receive clock input (SRCK0) Bit 12—PA12 Mode Bit (PA12MD): Selects the function of pin PA12/SRS0. Bit 12: PA12MD Description General input/output (PA12)
Page 811 Section 19 Pin Function Controller (PFC) Bit 7—PA7 Mode Bit (PA7MD): Selects the function of pin WDTOVF/PA7. Bit 7: PA7MD Description WDT overflow signal output (WDTOVF) * (Initial value) General input/output (PA7) Note: * WDTOVF is an output pin after a reset, so care is required when using this pin as a general input port (PA7).
Page 812: Port A I/O Register (Paior)
Section 19 Pin Function Controller (PFC) Bit 1—PA1 Mode Bit (PA1MD): Selects the function of pin PA1/EXOUT. Bit 1: PA1MD Description General input/output (PA1) (Initial value) EtherC general external output (EXOUT) Bit 0—PA0 Mode Bit (PA0MD): Selects the function of pin PA0. Bit 0: PA0MD Description General input/output (PA0)
Page 813: Port B Control Registers (Pbcr, Pbcr2)
Section 19 Pin Function Controller (PFC) 19.3.3 Port B Control Registers (PBCR, PBCR2) The port B control registers (PBCR and PBCR2) are 16-bit read/write registers that select the functions of the 16 multiplex pins in port B. PBCR selects the functions of the pins for the upper 8 bits in port B, and PBCR2 selects the functions of the pins for the lower 8 bits in port B.
Page 814 Section 19 Pin Function Controller (PFC) Bits 13 and 12—PB14 Mode Bits 1 and 0 (PB14MD1, PB14MD0): These bits select the function of pin PB14/RXD1. Bit 13: PB14MD1 Bit 12: PB14MD0 Description General input/output (PB14) (Initial value) Reserved SCIF1 serial data input (RXD1) Reserved Bits 11 and 10—PB13 Mode Bits 1 and 0 (PB13MD1, PB13MD0): These bits select the function of pin PB13/TXD1.
Page 815 Section 19 Pin Function Controller (PFC) Bits 5 and 4—PB10 Mode Bits 1 and 0 (PB10MD1, PB10MD0): These bits select the function of pin PB10/SRXD2/TIOCA1. Bit 5: PB10MD1 Bit 4: PB10MD0 Description General input/output (PB10) (Initial value) SIO2 serial receive data input (SRXD2) TPU1 input capture input/output compare output (TIOCA1) Reserved...
Page 816 Section 19 Pin Function Controller (PFC) Port B Control Register 2 (PBCR2) Bit: Initial value: R/W: Bit: Initial value: R/W: Bits 15 and 14—PB7 Mode Bits 1 and 0 (PB7MD1, PB7MD0): These bits select the function of pin PB7/STXD2/TIOCB2, TCLKD. Bit 15: PB7MD1 Bit 14: PB7MD0 Description...
Page 817 Section 19 Pin Function Controller (PFC) Bits 11 and 10—PB5 Mode Bits 1 and 0 (PB5MD1, PB5MD0): These bits select the function of pin PB5/SRS1/RXD2. Bit 11: PB5MD1 Bit 10: PB5MD0 Description General input/output (PB5) (Initial value) SIO1 serial receive synchronous input (SRS1) SCIF2 serial data input (RXD2) Reserved Bits 9 and 8—PB4 Mode Bits 1 and 0 (PB4MD1, PB4MD0): These bits select the function of pin...
Page 818 Section 19 Pin Function Controller (PFC) Bits 3 and 2—PB1 Mode Bits 1 and 0 (PB1MD1, PB1MD0): These bits select the function of pin PB1/STXD1/TIOCC0/TCLKA. Bit 3: PB1MD1 Bit 2: PB1MD0 Description General input/output (PB1) (Initial value) SIO1 serial transmit data output (STXD1) TPU0 input capture input/output compare output (TIOCC0) * Reserved...
Page 819: Port B I/O Register (Pbior)
Section 19 Pin Function Controller (PFC) 19.3.4 Port B I/O Register (PBIOR) Bit: PB15 PB14 PB13 PB12 PB11 PB10 Initial value: R/W: Bit: Initial value: R/W: The port B I/O register (PBIOR) is a 16-bit read/write register that selects the input/output direction of the 16 multiplex pins in port B.
Page 820 Section 19 Pin Function Controller (PFC) Rev. 2.00 Mar 09, 2006 page 794 of 906 REJ09B0292-0200...
Page 821: Section 20 I/O Ports
Section 20 I/O Ports Section 20 I/O Ports 20.1 Overview This chip has two ports, designated A and B. Port A is a 14-bit input/output port, and port B is a 16-bit input/output port. The port pins are multiplexed as general input/output and other functions. (The function of multiplexed multiplex pins is selected by means of the pin function controller (PFC).) Ports A and B are each provided with a data register for storing pin data.
Page 822: Register Configuration
Section 20 I/O Ports 20.2.1 Register Configuration The port A register is shown in table 20.1. Table 20.1 Register Configuration Name Abbreviation Initial Value Address Access Size Port A data register PADR H'0000 H'FFFFFC84 8, 16 20.2.2 Port A Data Register (PADR) Bit: —...
Page 823: Port B
Section 20 I/O Ports Table 20.2 Port A Data Register (PADR) Read/Write Operations PAIOR Pin Function Read Write General input Pin state Value is written to PADR, but does not affect pin state Other than general input Pin state Value is written to PADR, but does not affect pin state General output PADR value...
Page 824: Port B Data Register (Pbdr)
Section 20 I/O Ports Table 20.3 Register Configuration Name Abbreviation Initial Value Address Access Size Port B data register PBDR H'0000 H'FFFFFC8C 8, 16 20.3.2 Port B Data Register (PBDR) Bit: PB15DR PB14DR PB13DR PB12DR PB11DR PB10DR PB9DR PB8DR Initial value: R/W: Bit: PB7DR...
Page 825: Section 21 Power-Down Modes
Section 21 Power-Down Modes Section 21 Power-Down Modes 21.1 Overview This chip has a module standby function (which reduces power consumption by selectively halting operation of unnecessary modules among the on-chip peripheral modules and the DSP unit), a sleep mode (which halts CPU functions), and a standby mode (which halts all functions). 21.1.1 Power-Down Modes The following modes and function are provided as power-down modes:...
Page 826: Register
Section 21 Power-Down Modes Table 21.1 Power-Down Modes State On-Chip Oscilla- UBC, DMAC, tion FRT, Circuit, SCIF1–2, Transition E-DMAC, CPU, TPU, SIOF, Canceling Mode Condition EtherC Cache DSP SIO1–2 Pins Procedure 1. Interrupt Sleep SLEEP Runs Halted Halted Runs Runs Runs mode instruction...
Page 827: Register Descriptions
Section 21 Power-Down Modes 21.2 Register Descriptions 21.2.1 Standby Control Register 1 (SBYCR1) Bit: MSTP5 MSTP4 MSTP3 — MSTP1 — (UBC) (DMAC) (DSP) (FRT) Initial value: R/W: Standby control register 1 (SBYCR1) is an 8-bit read/write register that sets the power-down mode.
Page 828 Section 21 Power-Down Modes Bit 4—Module Stop 4 (MSTP4): Specifies halting the clock supply to the DMAC. When MSTP4 bit is set to 1, the supply of the clock to the DMAC is halted. When the clock halts, the DMAC retains its pre-halt state.
Page 829: Standby Control Register 2 (Sbycr2)
Section 21 Power-Down Modes 21.2.2 Standby Control Register 2 (SBYCR2) Bit: — — MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 (TPU) (SIO2) (SIO1) (SIOF) (SCIF2) (SCIF1) Initial value: R/W: Standby control register 2 (SBYCR2) is an 8-bit read/write register that sets the power-down mode state.
Page 830 Section 21 Power-Down Modes Bit 3—Module Stop 9 (MSTP9): Specifies halting the clock supply to SIO channel 1. When the MSTP9 bit is set to 1, the supply of the clock to SIO channel 1 is halted. When the clock halts, SIO channel 1 retains its pre-halt state, and the SIO channel 1 interrupt vector register in the INTC retains its pre-halt value.
Page 831: Sleep Mode
Section 21 Power-Down Modes 21.3 Sleep Mode 21.3.1 Transition to Sleep Mode Executing the SLEEP instruction when the SBY bit in SBYCR1 is 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged.
Page 832 Section 21 Power-Down Modes Table 21.3 Register States in Standby Mode Registers Registers that Retain with Undefined Module Registers Initialized Data Contents Interrupt controller (INTC) — All registers — User break controller (UBC) — All registers — Bus state controller (BSC) —...
Page 833: Canceling Standby Mode
Section 21 Power-Down Modes 21.4.2 Canceling Standby Mode Standby mode is canceled by an NMI interrupt, a power-on reset, or a manual reset. Cancellation by an NMI Interrupt: When a rising edge or falling edge is detected in the NMI signal, after the elapse of the time set in the WDT timer control/status register, clocks are supplied to the entire chip, standby mode is canceled, and NMI exception handling begins.
Page 834: Clock Pause Function
Section 21 Power-Down Modes Oscillator CKIO (output) NMIE Oscillation settling time exception handling Standby mode set time Exception NMI exception Start of service routine, handling oscillation SBY = 1, SLEEP instruction Figure 21.1 Standby Mode Cancellation by NMI Interrupt 21.4.4 Clock Pause Function When the clock is input from the CKIO pin, the clock frequency can be modified or the clock stopped.
Page 835 Section 21 Power-Down Modes 6. When PLL circuit 1 is operational, the WDT starts counting up inside the chip. When PLL circuit 1 is halted, the WDT is not activated. When the internal clock stabilizes, the CKPACK pin goes high, giving external notification that the chip can be operated.
Page 836 Section 21 Power-Down Modes Figure 21.3 shows the clock pause function timing chart when the PLL circuit is halted. Frequency modification CKIO input CKPREQ/ CKM input Clock pause request cancellation CKPACK output Normal state Clock pause state Clock pause acceptance processing Figure 21.3 Clock Pause Function Timing Chart (PLL Circuit 1 Halted) The clock pause state can be canceled by means of NMI input, in the same way as the normal...
Page 837: Notes On Standby Mode
Section 21 Power-Down Modes Frequency modification Max. 4 cycles CKIO input CKPREQ/ CKM input Clock pause request NMI input cancellation NMI interrupt CKPACK output Clock pause state Normal state Clock pause acceptance processing Figure 21.4 Clock Pause Function Timing Chart (Cancellation by NMI Input) 21.4.5 Notes on Standby Mode 1.
Page 838: Module Standby Function
Section 21 Power-Down Modes 21.5 Module Standby Function 21.5.1 Transition to Module Standby Function By setting one of bits MSTP11–MSTP3, MSTP1 to 1 in standby control register 1 or 2, the supply of the clock to the corresponding on-chip peripheral module or DSP unit can be halted. This function can be used to reduce the power consumption.
Page 839: Section 22 Electrical Characteristics
Section 22 Electrical Characteristics Section 22 Electrical Characteristics 22.1 Absolute Maximum Ratings Table 22.1 shows the absolute maximum ratings. Table 22.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage (internal) –0.3 to +4.2 Power supply voltage (5 V I/O) –0.3 to +7.0 Input voltage (excluding 5 V I/O) –0.3 to V...
Page 840: Dc Characteristics
Section 22 Electrical Characteristics 22.2 DC Characteristics Tables 22.2 and 22.3 show the DC characteristics. Table 22.2 DC Characteristics ≥ ≥ ≥ ≥ V Conditions: V = PLLV = 3.3 V ±0.3 V, PV = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PV = PV = PLLV = 0 V, Ta = –20 to +75°C...
Page 841 Section 22 Electrical Characteristics ≥ ≥ ≥ ≥ V Conditions: V = PLLV = 3.3 V ±0.3 V, PV = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PV = PV = PLLV = 0 V, Ta = –20 to +75°C Item Symbol Min Typ Max...
Page 842: Ac Characteristics
Section 22 Electrical Characteristics 22.3 AC Characteristics In principle, input is synchronous. Unless specified otherwise, ensure that the setup time and hold times for each input signal are observed. Table 22.4 Maximum Operating Frequencies ≥ V Conditions: V = PLLV = 3.3 V ±0.3 V, PV = 5.0 V ±...
Page 843: Clock Timing
Section 22 Electrical Characteristics 22.3.1 Clock Timing Table 22.5 Clock Timing ≥ ≥ ≥ ≥ V Conditions: V = PLLV = 3.3 V ±0.3 V, PV = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PV = PV = PLLV = 0 V, Ta = –20 to +75°C Item Symbol...
Page 844 Section 22 Electrical Characteristics EXcyc EXTAL* 1/2 V 1/2 V (input) Note: * When clock is input from EXTAL pin Figure 22.1 EXTAL Clock Input Timing CKIcyc CKIH CKIL CKIO 1/2 V 1/2 V (input) CKIR CKIF Figure 22.2 CKIO Clock Input Timing CKOH CKOL CKIO...
Page 845 Section 22 Electrical Characteristics Stable oscillation CKIO, internal clock Vcc min RESW OSC1 Note: Oscillation stabilization time when using on-chip crystal oscillator Figure 22.4 Power-On Oscillation Stabilization Time at Power-On Stable oscillation Standby CKIO, internal clock RESW OSC2 Note: Oscillation stabilization time when using on-chip crystal oscillator Figure 22.5 Oscillation Stabilization Time after Standby Recovery (Recovery by RES RES) Rev.
Page 846 Section 22 Electrical Characteristics Stable oscillation Standby CKIO, internal clock OSC3 Note: Oscillation stabilization time when using on-chip crystal oscillator Figure 22.6 Oscillation Stabilization Time after Standby Recovery (Recovery by NMI) Change of oscillation frequency Stable oscillation Stable oscillation EXTAL or CKIO PLL synchronization PLL synchronization...
Page 847: Control Signal Timing
Section 22 Electrical Characteristics 22.3.2 Control Signal Timing Table 22.6 Control Signal Timing ≥ ≥ ≥ ≥ V Conditions: V = PLLV = 3.3 V ±0.3 V, PV = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PV = PV = PLLV = 0 V, Ta = –20 to +75°C Item...
Page 848 Section 22 Electrical Characteristics CKIO RESS NMIH NMIS IRLH IRLS IRL3–IRL0 Figure 22.9 Interrupt Signal Input Timing CKIO BLSS BLSS BLSH BLSH BRLS (input) BGRD BGRD (output) BOFF RD, RD/WR, RAS, CAS, CSn, WEn, BS, IVECF BOFF A24–A0, D31–D0 Figure 22.10 Bus Release Timing Rev.
Page 849: Bus Timing
Section 22 Electrical Characteristics 22.3.3 Bus Timing Table 22.7 PLL-On Bus Timing [Modes 0 and 4] (1) ≥ ≥ ≥ ≥ V Conditions: V = PLLV = 3.3 V ±0.3 V, PV = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PV = PV = PLLV = 0 V, Ta = –20 to +75°C...
Page 850 Section 22 Electrical Characteristics ≥ ≥ ≥ ≥ V Conditions: V = PLLV = 3.3 V ±0.3 V, PV = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PV = PV = PLLV = 0 V, Ta = –20 to +75°C Item Symbol Min Unit...
Page 851 Section 22 Electrical Characteristics Table 22.7 PLL-On Bus Timing [Modes 0 and 4] (2) ≥ ≥ ≥ ≥ V Conditions: V = PLLV = 3.3 V ±5%, PV = 5.0 V ±5%/3.3 V ±5%, PV = PV = PLLV = 0 V, Ta = –5 to +70°C, SDRAM bus cycle Item Symbol Unit...
Page 852 Section 22 Electrical Characteristics CKIO A24–A0 CSD2 CSD1 RD/WR RSD1 RSD1 WED1 WED1 ⋅ DQMxx RDH2 RDS1 D31–D0 DACD1 DACD2 DACKn* WAIT ⋅ is measured from the rise of CSn or RD, whichever comes first. Notes: 1. t RDH2 2. DACKn waveform when active-high is specified Figure 22.11 Basic Read Cycle (No Wait) Rev.
Page 853 Section 22 Electrical Characteristics CKIO A24–A0 CSD1 CSD2 RD/WR RSD1 RSD1 WED1 WED1 ⋅ DQMxx WDD1 WDH1 D31–D0 DACD1 DACD2 DACKn* WAIT ⋅ Note: * DACKn waveform when active-high is specified Figure 22.12 Basic Write Cycle (No Wait) Rev. 2.00 Mar 09, 2006 page 827 of 906 REJ09B0292-0200...
Page 854 Section 22 Electrical Characteristics CKIO A24–A0 RD/WR ⋅ DQMxx D31–D0 DACKn* WAIT ⋅ Note: * DACKn waveform when active-high is specified Figure 22.13 Basic Bus Cycle (1 Wait Cycle) Rev. 2.00 Mar 09, 2006 page 828 of 906 REJ09B0292-0200...
Page 855 Section 22 Electrical Characteristics CKIO A24–A0 RD/WR ⋅ DQMxx D31–D0 DACKn* WAIT ⋅ Note: * DACKn waveform when active-high is specified Figure 22.14 Basic Bus Cycle (External Wait Input) Rev. 2.00 Mar 09, 2006 page 829 of 906 REJ09B0292-0200...
Page 856 Section 22 Electrical Characteristics CKIO Address upper bits Address lower bits CSD1 CSD1 RD/WR RSD1 DQMD DQMD ⋅ DQMxx RDS3 RDS3 RDS3 RDH4 RDS3 RDH4 RDH4 RDH4 D31–D0 DACD1 DACD1 DACKn* WAIT RASD1 RASD1 RASD1 CASD1 CASD1 CASD1 CASD1 CAS · Notes: 1.
Page 857 Section 22 Electrical Characteristics CKIO Address upper bits Address lower bits CSD1 CSD1 RD/WR RSD1 DQMD DQMD DQMD ⋅ DQMxx RDS3 RDH4 D31–D0 DACKn* WAIT RASD1 RASD1 RASD1 CASD1 CASD1 CASD1 CASD1 ⋅ Notes: 1. Dotted line shows the case where synchronous DRAM in a different CS space is accessed.
Page 858 Section 22 Electrical Characteristics CKIO Address upper bits Address lower bits RD/WR ⋅ DQMxx – DACKn* WAIT RASD1 RASD1 CASD1 CASD1 – Notes: 1. Dotted line shows the case where synchronous DRAM in a different CS space is accessed. 2. DACKn waveform when active-high is specified Figure 22.17 Synchronous DRAM Read Bus Cycle (RCD = 2 Cycles, CAS Latency = 2 Cycles, Burst = 4) Rev.
Page 859 Section 22 Electrical Characteristics CKIO Address upper bits Address lower bits CSD1 RD/WR DQMD ⋅ DQMxx D31–D0 DACD1 DACKn* WAIT RASD1 CASD1 CASD1 CASD1 CASD1 Note: * DACKn waveform when active-high is specified Figure 22.18 Synchronous DRAM Read Bus Cycle (Bank Active, Same Row Access, CAS Latency = 1 Cycle) Rev.
Page 860 Section 22 Electrical Characteristics CKIO Address upper bits Address lower bits RD/WR DQMD ⋅ DQMxx D31–D0 DACKn* WAIT ⋅ Note: * DACKn waveform when active-high is specified Figure 22.19 Synchronous DRAM Read Bus Cycle (Bank Active, Same Row Access, CAS Latency = 2 Cycles) Rev.
Page 861 Section 22 Electrical Characteristics CKIO Address upper bits Address lower bits CSD1 RD/WR DQMD ⋅ DQMxx D31–D0 DACD1 DACKn* WAIT RASD1 RASD1 ⋅ Note: * DACKn waveform when active-high is specified Figure 22.20 Synchronous DRAM Read Bus Cycle (Bank Active, Different Row Access, TRP = 1 Cycle, RCD = 1 Cycle, CAS Latency = 1 Cycle) Rev.
Page 862 Section 22 Electrical Characteristics CKIO Address upper bits Address lower bits RD/WR ⋅ DQMxx D31–D0 DACKn* WAIT RASD1 RASD1 ⋅ Note: * DACKn waveform when active-high is specified Figure 22.21 Synchronous DRAM Read Bus Cycle (Bank Active, Different Row Access, TRP = 2 Cycles, RCD = 1 Cycle, CAS Latency = 1 Cycle) Rev.
Page 863 Section 22 Electrical Characteristics CKIO Address upper bits Address lower bits CSD1 CSD1 CSD1 RD/WR RSD1 DQMD DQMD ⋅ DQMxx WDD1 WDH1 D31–D0 DACD1 DACD1 DACD1 DACKn* WAIT RASD1 RASD1 RASD1 RASD1 CASD1 CASD1 CASD1 ⋅ Notes: 1. Dotted line shows the case where synchronous DRAM in a different CS space is accessed.
Page 864 Section 22 Electrical Characteristics CKIO Address upper bits Address lower bits CSD1 RD/WR ⋅ DQMxx D31–D0 DACKn* WAIT RASD1 RASD1 CASD1 ⋅ Notes: 1. Dotted line shows the case where synchronous DRAM in a different CS space is accessed. 2. DACKn waveform when active-high is specified Figure 22.23 Synchronous DRAM Write Bus Cycle (RASD = 0, RCD = 2 Cycles, TRWL = 2 Cycles) Rev.
Page 865 Section 22 Electrical Characteristics CKIO Address upper bits Address lower bits CSD1 CSD1 RD/WR DQMD DQMD ⋅ DQMxx WDD1 WDH1 D31–D0 DACD1 DACD1 DACKn* WAIT RASD1 CASD1 CASD1 ⋅ Note: * DACKn waveform when active-high is specified Figure 22.24 Synchronous DRAM Write Bus Cycle (Bank Active, Same Row Access, Iφ...
Page 866 Section 22 Electrical Characteristics CKIO Address upper bits Address lower bits CSD1 CSD1 RD/WR DQMD DQMD ⋅ DQMxx WDD2 WDH1 D31–D0 DACD1 DACD1 DACKn* WAIT RASD1 CASD1 CASD1 ⋅ Note: * DACKn waveform when active-high is specified Figure 22.25 Synchronous DRAM Write Cycle (Bank Active, Same Row Access, Iφ...
Page 867 Section 22 Electrical Characteristics CKIO Address upper bits Address lower bits RD/WR DQMD ⋅ DQMxx WDD1 WDH1 D31–D0 DACKn* WAIT CASD1 CASD1 ⋅ Note: * DACKn waveform when active-high is specified Figure 22.26 Synchronous DRAM Continuous Write Cycle (Bank Active, Same Row Access, Iφ φ φ φ :Eφ φ φ φ other than 1:1) Rev.
Page 868 Section 22 Electrical Characteristics CKIO Address upper bits Address lower bits RD/WR DQMD ⋅ DQMxx WDD2 WDH1 D31–D0 DACKn* WAIT CASD1 CASD1 ⋅ Note: * DACKn waveform when active-high is specified Figure 22.27 Synchronous DRAM Continuous Write Cycle (Bank Active, Same Row Access, Iφ φ φ φ :Eφ φ φ φ = 1:1) Rev.
Page 869 Section 22 Electrical Characteristics CKIO Address upper bits Address lower bits CSD1 RD/WR DQMD DQMD ⋅ DQMxx D31–D0 DACD1 DACKn* WAIT RASD1 CASD1 ⋅ Note: * DACKn waveform when active-high is specified Figure 22.28 Synchronous DRAM Write Bus Cycle (Bank Active, Different Row Access, TRP = 1 Cycle, RCD = 1 Cycle) Rev.
Page 870 Section 22 Electrical Characteristics CKIO Address upper bits Address lower bits RD/WR DQMD ⋅ DQMxx D31–D0 DACKn* WAIT RASD1 RASD1 ⋅ Note: * DACKn waveform when active-high is specified Figure 22.29 Synchronous DRAM Write Bus Cycle (Bank Active, Different Row Access, TRP = 2 Cycles, RCD = 2 Cycles) Rev.
Page 871 Section 22 Electrical Characteristics CKIO Address upper bits Address lower bits CSD1 CSD1 RD/WR ⋅ DQMxx D31–D0 DACKn WAIT RASD1 RASD1 RSD1 CASD1 CASD1 ⋅ Note: An auto-refresh cycle is always preceded by a precharge cycle. The number of cycles between the two is determined by the number of cycles specified by TRP.
Page 872 Section 22 Electrical Characteristics CKIO Address upper bits Address lower bits CSD1 RD/WR ⋅ DQMxx D31–D0 DACKn WAIT RASD1 CASD1 ⋅ Figure 22.31 Synchronous DRAM Auto-Refresh Cycle (Shown from Precharge Cycle, TRP = 1 Cycle, TRAS = 4 Cycles) Rev. 2.00 Mar 09, 2006 page 846 of 906 REJ09B0292-0200...
Page 873 Section 22 Electrical Characteristics CKIO Address upper bits Address lower bits CSD1 CSD1 RD/WR ⋅ DQMxx D31–D0 DACKn WAIT RASD1 RASD1 RASD1 CASD1 ⋅ CASD1 CKED CKED Note: A self-refresh cycle is always preceded by a precharge cycle. The number of cycles between the two is determined by the number of cycles specified by TRP.
Page 874 Section 22 Electrical Characteristics CKIO Address upper bits Address lower bits CSD1 CSD2 RD/WR RSD1 RSD1 RSD1 CASD2 CASD2 CASD2 CASxx RDH5 RDS1 D31–D0 DACD1 DACD2 DACKn* WAIT RASD2 RASD2 RASD2 ⋅ is measured from the rise of RD or CASxx, whichever comes first. Notes: 1.
Page 875 Section 22 Electrical Characteristics CKIO Address upper bits Address lower bits CSD2 CSD1 RD/WR RSD1 CASD2 CASD2 CASD2 CASxx WDD1 WDH1 D31–D0 DACD2 DACD1 DACKn* WAIT RASD2 RASD2 RASD2 ⋅ Note: * DACKn waveform when active-high is specified Figure 22.34 DRAM Write Cycle (TRP = 1 Cycle, RCD = 1 Cycle, No Wait) Rev.
Page 876 Section 22 Electrical Characteristics CKIO Address upper bits Address lower bits RD/WR CASxx D31–D0 DACKn* WAIT ⋅ Note: * DACKn waveform when active-high is specified Figure 22.35 DRAM Bus Cycle (TRP = 2 Cycles, RCD = 2 Cycles, 1 Wait) Rev.
Page 877 Section 22 Electrical Characteristics CKIO Address upper bits Address lower bits RD/WR CASxx D31–D0 DACKn* WAIT ⋅ Note: * DACKn waveform when active-high is specified Figure 22.36 DRAM Bus Cycle (TRP = 1 Cycle, RCD = 1 Cycle, External Wait Input) Rev.
Page 878 Section 22 Electrical Characteristics CKIO Address upper bits Address lower bits RD/WR RSD1 RSD1 CASD2 CASD2 CASxx RDH5 RDH5 RDS1 RDS1 D31–D0 DACD1 DACD2 DACKn* WAIT ⋅ is measured from the rise of RD or CASxx, whichever comes first. Notes: 1. t RDH5 2.
Page 879 Section 22 Electrical Characteristics CKIO Address upper bits Address lower bits RD/WR CASD2 CASD2 CASxx WDD1 WDH1 D31–D0 DACD1 DACD2 DACKn* WAIT ⋅ Note: * DACKn waveform when active-high is specified Figure 22.38 DRAM Burst Write Cycle (TRP = 1 Cycle, RCD = 1 Cycle, No Wait) Rev.
Page 880 Section 22 Electrical Characteristics CKIO Address upper bits Address lower bits CSD1 CSD2 RD/WR RSD1 RSD1 RSD1 CASD2 CASD2 CASD2 CASxx RDH6 RDS2 D31–D0 DACD1 DACD2 RDH7 DACKn* WAIT RASD2 RASD3 RASD2 OED1 OED2 ⋅ OED1 Notes: 1. DACKn waveform when active-high is specified is measured from the rise of RAS or CAS ·...
Page 881 Section 22 Electrical Characteristics CKIO Address upper bits Address lower bits RD/WR RSD1 RSD1 CASD2 CASD2 CASxx RDH6 RDH6 RDS2 RDS2 D31–D0 DACD1 DACD2 DACKn* WAIT ⋅ Note: * DACKn waveform when active-high is specified Figure 22.40 EDO Burst Read Cycle (TRP = 1 Cycle, RCD = 1 Cycle, No Wait) Rev.
Page 882 Section 22 Electrical Characteristics CKIO Address upper bits Address lower bits CSD1 CSD1 RD/WR CASD2 CASD2 CASD2 CASxx D31–D0 DACKn WAIT RASD2 RASD2 RASD2 ⋅ Figure 22.41 DRAM CAS CAS-Before-RAS RAS Refresh Cycle (TRP = 1 Cycle, TRAS = 2 Cycles) Rev.
Page 883 Section 22 Electrical Characteristics CKIO A24–A0 CSD1 CSD2 RD/WR RSD1 RSD1 RSD1 RSD1 CASD1 CASD1 CASxx RDH2 RDH2 RDS1 RDS1 D31–D0 DACD1 DACD1 DACD2 DACD2 DACKn* WAIT ⋅ Note: * DACKn waveform when active-high is specified Figure 22.42 Burst ROM Read Cycle (Wait = 1) Rev.
Page 884 Section 22 Electrical Characteristics CKIO A3–A0 IVECF RD/WR RSD1 RSD1 RDH8 RSD1 D7–D0 WAIT Figure 22.43 Interrupt Vector Fetch Cycle (No Wait, Iφ φ φ φ :Eφ φ φ φ = 1:1) Rev. 2.00 Mar 09, 2006 page 858 of 906 REJ09B0292-0200...
Page 885 Section 22 Electrical Characteristics CKIO A3–A0 IVECF RD/WR RSD1 RSD1 RSD1 RDH8 D7–D0 WAIT Figure 22.44 Interrupt Vector Fetch Cycle (No Wait, Iφ φ φ φ :Eφ φ φ φ other than 1:1) Rev. 2.00 Mar 09, 2006 page 859 of 906 REJ09B0292-0200...
Page 886 Section 22 Electrical Characteristics CKIO A3–A0 IVECF RD/WR D7–D0 WAIT Figure 22.45 Interrupt Vector Fetch Cycle (External Wait Input, Iφ φ φ φ :Eφ φ φ φ other than 1:1) CKIO REFOD REFOUT Figure 22.46 REFOUT Delay Time Rev. 2.00 Mar 09, 2006 page 860 of 906 REJ09B0292-0200...
Page 887: Direct Memory Access Controller Timing
Section 22 Electrical Characteristics 22.3.4 Direct Memory Access Controller Timing Table 22.8 Direct Memory Access Controller Timing ≥ ≥ ≥ ≥ V Conditions: V = PLLV = 3.3 V ±0.3 V, PV = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PV = PV = PLLV = 0 V, Ta = –20 to +75°C...
Page 888: Free-Running Timer Timing
Section 22 Electrical Characteristics 22.3.5 Free-Running Timer Timing Table 22.9 Free-Running Timer Timing ≥ ≥ ≥ ≥ V Conditions: V = PLLV = 3.3 V ±0.3 V, PV = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PV = PV = PLLV = 0 V, Ta = –20 to +75°C Item...
Page 889 Section 22 Electrical Characteristics CKIO FOCD FTOA, FTOB FICS FICH Figure 22.49 FRT Input/Output Timing (t other than 1:1) Ecyc Pcyc CKIO FCKS FTCI FCKWL FCKWH Figure 22.50 FRT Clock Input Timing (t = 1:1) Ecyc Pcyc CKIO FCKS FTCI FCKWL FCKWH Figure 22.51 FRT Clock Input Timing (t...
Page 890: Serial Communication Interface Timing
Section 22 Electrical Characteristics 22.3.6 Serial Communication Interface Timing Table 22.10 Serial Communication Interface Timing ≥ ≥ ≥ ≥ V Conditions: V = PLLV = 3.3 V ±0.3 V, PV = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PV = PV = PLLV = 0 V, Ta = –20 to +75°C...
Page 891 Section 22 Electrical Characteristics scyc (transmit data) (receive data) Figure 22.53 SCI Input/Output Timing (Synchronous Mode) scyc SCK1 RTSD CTSS CTSH Figure 22.54 RTS RTS and CTS CTS Input/Output Timing Rev. 2.00 Mar 09, 2006 page 865 of 906 REJ09B0292-0200...
Page 892 Section 22 Electrical Characteristics Table 22.11 16-Bit Timer-Pulse Unit ≥ ≥ ≥ ≥ V Conditions: V = PLLV = 3.3 V ±0.3 V, PV = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PV = PV = PLLV = 0 V, Ta = –20 to +75°C Item Symbol Unit...
Page 893 Section 22 Electrical Characteristics CKIO TOCD Output compare output* TICS Input capture input* Note: * TIOCA0–TIOCA2, TIOCB0–TIOCB2, TIOCC0, TIOCD0 Figure 22.56 TPU Input/Output Timing (t other than 1:1) Ecyc Pcyc CKIO TCKS TCKS TCLKA–TCLKD TCKWH TCKWL Figure 22.57 TPU Clock Input Timing Rev.
Page 894: Watchdog Timer Timing
Section 22 Electrical Characteristics 22.3.7 Watchdog Timer Timing Table 22.12 Watchdog Timer Timing ≥ ≥ ≥ ≥ V Conditions: V = PLLV = 3.3 V ±0.3 V, PV = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PV = PV = PLLV = 0 V, Ta = –20 to +75°C Item...
Page 895: Serial I/O With Fifo / Serial I/O Timing
Section 22 Electrical Characteristics 22.3.8 Serial I/O with FIFO / Serial I/O Timing Table 22.13 Serial I/O with FIFO / Serial I/O Timing ≥ ≥ ≥ ≥ V Conditions: V = PLLV = 3.3 V ±0.3 V, PV = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PV = PV = PLLV = 0 V, Ta = –20 to +75°C...
Page 896 Section 22 Electrical Characteristics [SIOF] SFcyc SFWL STCK0, SRCK0 SFWH [SIO] SIcyc STCKn, SRCKn n = 1 or 2 Figure 22.60 SIOF / SIO Input Clock Timing SRCKn (input) SRDS SRDH SRSn (input) SRXDn (input) n = 0, 1, or 2 Figure 22.61 SIOF / SIO Receive Timing Rev.
Page 897 Section 22 Electrical Characteristics [SIOF] STCK0 (input) SFTSS STS0 (input) STXD0 (output) [SIO] STCKn (input) STSn (input) STXDn (output) n = 1, or 2 Figure 22.62 SIOF / SIO Transmit Timing (TMn = 0 Mode) STCKn (input) STSn (output) STXDn (output) n = 0, 1, or 2 Figure 22.63 SIOF / SIO Transmit Timing (TMn = 1 Mode)
Page 898: User Debug Interface Timing
Section 22 Electrical Characteristics 22.3.9 User Debug Interface Timing Table 22.14 User Debug Interface Timing ≥ ≥ ≥ ≥ V Conditions: V = PLLV = 3.3 V ±0.3 V, PV = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PV = PV = PLLV = 0 V, Ta = –20 to +75°C...
Page 899: I/O Port Timing
Section 22 Electrical Characteristics TMSS TMSH TDIS TDIH TDOD TDOD Figure 22.66 H-UDI Input/Output Timing 22.3.10 I/O Port Timing Table 22.15 I/O Port Timing ≥ ≥ ≥ ≥ V Conditions: V = PLLV = 3.3 V ±0.3 V, PV = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PV = PV = PLLV = 0 V, Ta = –20 to +75°C...
Page 900 Section 22 Electrical Characteristics CKIO PA13 – PB15 – (read) PA13 – PB15 – (write) Figure 22.67 I/O Port Input/Output Timing (t = 1:1) Ecyc Pcyc CKIO PA13 – PB15 – (read) PA13 – PB15 – (write) ≠ ≠ ≠ ≠ 1:1) Figure 22.68 I/O Port Input/Output Timing (t Ecyc Pcyc...
Page 901 Section 22 Electrical Characteristics 22.3.11 Ethernet Controller Timing Table 22.16 Ethernet Controller Timing ≥ ≥ ≥ ≥ V Conditions: V = PLLV = 3.3 V ±0.3 V, PV = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PV = PV = PLLV = 0 V, Ta = –20 to +75°C Item...
Page 902 Section 22 Electrical Characteristics TX – CLK TENd TX – EN ETDd Preamble DATA ETXD[3:0] TX – ER CRSh CRSs Figure 22.69 MII Send Timing (Normal Operation) TX – CLK TX – EN Preamble ETXD[3:0] TX – ER COLs COLh Figure 22.70 MII Send Timing (Case of Conflict) RX –...
Page 903 Section 22 Electrical Characteristics RX – CLK RX – DV Preamble DATA XXXX ERXD[3:0] RERs RERh RX – ER Figure 22.72 MII Receive Timing (Case of Error) MDIOh MDIOs MDIO Figure 22.73 MDIO Input Timing MDIOdh MDIO Figure 22.74 MDIO Output Timing RX –...
Page 904 Section 22 Electrical Characteristics RX – CLK RX – DV Preamble Dest Address Source Address DATA ERXD[3:0] CAMS CAMh CAMSEN Figure 22.77 CAMSEN Input Timing 22.3.12 STATS, BH BH, and BUSHiZ BUSHiZ Signal Timing BUSHiZ BUSHiZ Table 22.17 STATS, BH BH, and BUSHiZ BUSHiZ Signal Timing BUSHiZ...
Page 905 Section 22 Electrical Characteristics CKI0 Read0 Read1 Read2 Read3 Write0 Write1 Write2 Write3 Address G-DMAC G-DMAC G-DMAC G-DMAC G-DMAC G-DMAC G-DMAC G-DMAC BHNfd BHNrd Figure 22.79 BH BH Output Timing CKI0 WAIT BHIZs BHIZh BUSHiZ BHIZd Target Pins Figure 22.80 BUSHiZ BUSHiZ BUSHiZ BUSHiZ Bus Timing...
Page 906 • Input pulse level: Vss to 3.0 V (Vss to Vcc for RES, TRST, EXTAL, CKIO, MD0–MD4, and NMI) • Input rise/fall time: 1 ns The output load circuit is shown in figure 22.81. SH7616 DUT output output pin is the total value, including the capacitance of the test jig, etc. The capacitance of each pin is as follows: 30 pF: CKIO, A24–A0, D31–D0, BS, RD, CS4–CS0, DQMUU/WE3–DQMLL/WE0, CAS3–CAS0,...
Page 907 Appendix A On-Chip Peripheral Module Registers Appendix A On-Chip Peripheral Module Registers Addresses On-chip peripheral module register addresses and bit names are shown in the following table. 16- bit registers and 32-bit registers are shown, respectively, in two and four lines of 8 bits. Bit Names Register Address...
Page 908 Appendix A On-Chip Peripheral Module Registers Bit Names Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFFC20 SIRDR2 SIO2 H'FFFFFC21 H'FFFFFC22 SITDR2 H'FFFFFC23 H'FFFFFC24 SICTR2 — — — —...
Page 909 Appendix A On-Chip Peripheral Module Registers Bit Names Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFFC66 TCNT1 H'FFFFFC67 H'FFFFFC68 TGR1A H'FFFFFC69 H'FFFFFC6A TGR1B H'FFFFFC6B H'FFFFFC6C — — —...
Page 910 Appendix A On-Chip Peripheral Module Registers Bit Names Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFFC8C PBDR PB15DR PB14DR PB13DR PB12DR PB11DR PB10DR PB9DR PB8DR I/O port H'FFFFFC8D PB7DR PB6DR...
Page 911 Appendix A On-Chip Peripheral Module Registers Bit Names Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFF FCD2 SCFER1 ED15 ED14 ED13 ED12 ED11 ED10 SCIF1 H'FFFF FCD3 H'FFFF FCD4 SCIMR1 IRMOD PSEL...
Page 912 Appendix A On-Chip Peripheral Module Registers Bit Names Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFF FD00 EDMR — — — — — — — — E-DMAC H'FFFF FD01 —...
Page 913 Appendix A On-Chip Peripheral Module Registers Bit Names Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFF FD20 RMFCR — — — — — — — — E-DMAC H'FFFF FD21 —...
Page 914 Appendix A On-Chip Peripheral Module Registers Bit Names Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFF FD48 — — — — — — — — — E-DMAC H'FFFF FD4B H'FFFF FD4C TBRAR TBRA31...
Page 915 Appendix A On-Chip Peripheral Module Registers Bit Names Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFF FD74 MALR — — — — — — — — EtherC H'FFFF FD75 —...
Page 916 Appendix A On-Chip Peripheral Module Registers Bit Names Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFF FD94 CEFCR — — — — — — — — EtherC H'FFFF FD95 —...
Page 917 Appendix A On-Chip Peripheral Module Registers Bit Names Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFF FDB8 — — — — — — — — — — H'FFFF FE0F H'FFFFFE10 TIER...
Page 918 Appendix A On-Chip Peripheral Module Registers Bit Names Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFFE54 VCRN — SER2V6 SER2V5 SER2V4 SER2V3 SER2V2 SER2V1 SER2V0 INTC H'FFFFFE55 —...
Page 919 Appendix A On-Chip Peripheral Module Registers Bit Names Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFFE94 — — — — — — — — — — H'FFFFFEBF H'FFFFFEC0 IPRE SCF2IP3 SCF2IP2 SCF2IP1 SCF2IP0 SIOFIP3 SIOFIP2 SIOFIP1 SIOFIP0 INTC...
Page 920 Appendix A On-Chip Peripheral Module Registers Bit Names Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFF FF04 BAMRAH BAMA31 BAMA30 BAMA29 BAMA28 BAMA27 BAMA26 BAMA25 BAMA24 UBC H'FFFF FF05 BAMA23 BAMA22 BAMA21 BAMA20 BAMA19 BAMA18 BAMA17 BAMA16 H'FFFF FF06...
Page 921 Appendix A On-Chip Peripheral Module Registers Bit Names Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFF FF2A — — — — — — — — — — H'FFFF FF2F H'FFFF FF30 BRCRH...
Page 922 Appendix A On-Chip Peripheral Module Registers Bit Names Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFF FF60 BARDH BAD31 BAD30 BAD29 BAD28 BAD27 BAD26 BAD25 BAD24 H'FFFF FF61 BAD23 BAD22 BAD21...
Page 923 Appendix A On-Chip Peripheral Module Registers Bit Names Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFFF88 TCR0 — — — — — — — — DMAC H'FFFFFF89 H'FFFFFF8A H'FFFFFF8B H'FFFFFF8C...
Page 924 Appendix A On-Chip Peripheral Module Registers Bit Names Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFFFB0 DMAOR — — — — — — — — DMAC H'FFFFFFB1 —...
Page 925 Appendix A On-Chip Peripheral Module Registers Bit Names Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFFFF2 — — — — — — — — — — H'FFFFFFF3 H'FFFFFFF4 RTCNT —...
Page 926: Appendix B Pin States
Appendix B Pin States Appendix B Pin States Pin States in Reset, Power-Down State, and Bus-Released State Pin State Manual Reset Power-Down State Power- Standby Standby Bus- Mode Mode Sleep Released Pin Type Pin Name Reset Acquired Released (HIZ = 0) (HIZ = 1) Mode State...
Page 927 Appendix B Pin States Pin State Manual Reset Power-Down State Power- Standby Standby Bus- Mode Mode Sleep Released Pin Type Pin Name Reset Acquired Released (HIZ = 0) (HIZ = 1) Mode State Clock XTAL EXTAL CKIO CKPACK CKPREQ/CKM PLLCAP2, PLLCAP1 DMAC DREQ1, DREQ0 DACK1, DACK0...
Page 928 Appendix B Pin States Pin State Manual Reset Power-Down State Power- Standby Standby Bus- Mode Mode Sleep Released Pin Type Pin Name Reset Acquired Released (HIZ = 0) (HIZ = 1) Mode State Port, PB0/TIOCD0, IO/Z/O IO/Z/O K/K/O IO/IO/O IO/IO/O Internal TCLKB/WOL peripheral PA13/SRCK0...
Page 929 Appendix B Pin States Pin State Manual Reset Power-Down State Power- Standby Standby Bus- Mode Mode Sleep Released Pin Type Pin Name Reset Acquired Released (HIZ = 0) (HIZ = 1) Mode State EtherC TX-CLK TX-EN TX-ER ETXD–ETXD0 MDIO RX-CLK RX-DV RX-ER ERXD–ERXD0...
Page 930: Appendix C Product Lineup
Appendix C Product Lineup Appendix C Product Lineup Table C.1 SH7616 Product Lineup Operating Abbreviation Voltage Frequency Mark Code Package SH7616 3.3 V 62.5 MHz HD6417616SF PLQP0208KA-A Rev. 2.00 Mar 09, 2006 page 904 of 906 REJ09B0292-0200...
Page 931: Appendix D Package Dimensions
Appendix D Package Dimensions Appendix D Package Dimensions Figure D.1 shows the PLQP0208KA-A package dimensions. JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-LQFP208-28x28-0.50 PLQP0208KA-A FP-208C/FP-208CV 2.7g NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
Page 932 Appendix D Package Dimensions Rev. 2.00 Mar 09, 2006 page 906 of 906 REJ09B0292-0200...
Page 933 Publication Date: 1st Edition, November 2001 Rev.2.00, March 09, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. ©2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Page 934 Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Page 935 SH7616 Hardware Manual...

This manual is also suitable for:

Sh7600 series

Renesas SH7616 Hardware Manual

Section 1 Overview

Section 2 CPU

Section 3 Oscillator Circuits and Operating Modes

Section 4 Exception Handling

Section 5 Interrupt Controller (INTC)

Section 6 User Break Controller (UBC)

Appendix A On-Chip Peripheral Module Registers

Section 7 Bus State Controller (BSC)

Section 8 Cache

Section 9 Ethernet Controller (Etherc)

Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC)

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