Renesas SH7040 Series Supplementary Information page 11

Renesas microcomputer development environment system
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Figures
Figure 2.1 Default User System Interface Circuit...................................................................... 7
Figure 2.2 User System Interface Circuit for Mode Pins........................................................... 8
Figure 2.3 User System Interface Circuit for RES and NMI ..................................................... 8
Figure 2.4 User System Interface Circuit for PF0/AN0-PF7/AN7, PA0-PA4, PE5/TIOC1B ... 9
Figure 2.5 User System Interface Circuit for IRQ0-IRQ7 and WDTOVF ............................... 9
Figure 2.6 User System Interface Circuit for AVcc, AVss, and AVref ..................................... 10
Figure 2.7 User System Interface Circuit for XTAL and EXTAL ............................................ 10
Tables
Table 1.1 Environment Conditions........................................................................................... 1
Table 1.2 User System Interface Cables for SH7040 ............................................................... 2
Table 1.4 Operating Voltage and Frequency Specifications..................................................... 4
Table 1.5 Clock Selections for E6000 SH7040 Emulator ........................................................ 5
Table 4.1 Address Area Parameters.......................................................................................... 12
Table 4.2 Bus Status Parameters............................................................................................... 13
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