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0839G–08/01
Figure 47. Port D Schematic Diagram (Pins PD4 and PD5)
MOS
PULL-
UP
PDn
WP:
WRITE PORTD
WD:
WRITE DDRD
RL:
READ PORTD LATCH
RP:
READ PORTD PIN
RD:
READ DDRD
n:
4, 5
m:
0, 1
Figure 48. Port D Schematic Diagram (Pin PD6)
RESET
Q
DDDn
WD
RESET
Q
PORTDn
RL
WP
RP
SENSE CONTROL
CSm0
CSm2
CSm1
AT90S2313
RD
R
D
C
R
D
C
TIMERm CLOCK
SOURCE MUX
61
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