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Timer/Counter1 – TCNT1H
and TCNT1L
0839G–08/01
• Bit 3 – CTC1: Clear Timer/Counter1 on Compare Match
When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock
cycle after a compareA match. If the CTC1 control bit is cleared, Timer/Counter1 contin-
ues counting and is unaffected by a compare match. Since the compare match is
detected in the CPU clock cycle following the match, this function will behave differently
when a prescaling higher than 1 is used for the timer. When a prescaling of 1 is used,
and the compareA register is set to C, the timer will count as follows if CTC1 is set:
... | C-2 | C-1 | C | 0 | 1 |...
When the prescaler is set to divide by 8, the timer will count like this:
... | C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, 0,
0, 0, 0, 0, 0, 0 |...
In PWM mode, this bit has no effect.
• Bits 2,1,0 – CS12, CS11, CS10: Clock Select1, Bits 2, 1 and 0
The Clock Select1 bits 2, 1 and 0 define the prescaling source of Timer/Counter1.
Table 10. Clock 1 Prescale Select
CS12
CS11
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
The Stop condition provides a Timer Enable/Disable function. The CK down divided
modes are scaled directly from the CK oscillator clock. If the external pin modes are
used for Timer/Counter1, transitions on PD5/(T1) will clock the counter even if the pin is
configured as an output. This feature can give the user software control of the counting.
Bit
15
14
$2D ($4D)
MSB
$2C ($4C)
7
6
Read/Write
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To
ensure that both the high and low bytes are read and written simultaneously when the
CPU accesses these registers, the access is performed using an 8-bit temporary regis-
ter (TEMP). This temporary register is also used when accessing OCR1A and ICR1. If
the main program and interrupt routines perform access to registers using TEMP, inter-
CS10
Description
0
Stop, the Timer/Counter1 is stopped.
1
CK
0
CK/8
1
CK/64
0
CK/256
1
CK/1024
0
External Pin T1, falling edge
1
External Pin T1, rising edge
13
12
11
5
4
3
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
AT90S2313
10
9
8
TCNT1H
LSB
TCNT1L
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
33
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